soc/intel/common: Set controller state to active in GSPI init

Set the controller state to D0 during the GSPI sequence,this ensures
the controller is up and active.

BUG=b:135941367
TEST=Verify no timeouts seen during GSPI controller enumeration
     sequence for CML and ICL platforms.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>

0 files changed, 0 insertions, 0 deletions