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| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2020-03-05 17:37:05 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-19 12:02:47 +0000 |
| commit | 44eeed0e5cbb1d449d2398671b29bb36b661ac6f (patch) | |
| tree | 4350d6bd09f796cb0c3410e547623f41be11ed79 /util/futility | |
| parent | 81877365d5a7d7f839957714c8fbeb9863d6c564 (diff) | |
| download | coreboot-44eeed0e5cbb1d449d2398671b29bb36b661ac6f.tar.xz | |
soc/intel/tigerlake: add support to read SPD data from SMBus
Jasper Lake RVP has DDR4 variant which uses SMBus address to read SPD
data. So, add support to read SPD data from SMBUS.
BUG=None
BRANCH=None
TEST=Check compilation for Jasper Lake RVP and check memory training passes.
Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39401
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/futility')
0 files changed, 0 insertions, 0 deletions