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| author | Subrata Banik <subrata.banik@intel.com> | 2019-02-25 20:31:22 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-07 17:21:44 +0000 |
| commit | 2847e1e71495158f1af02465fd6083674d767897 (patch) | |
| tree | 1fa5d292e2e7e813637062fbabb85c34916667b0 /util/intelmetool/intelmetool.c | |
| parent | 4f42eead361b8d6b2f96031bcaf4627f2a5ea8a6 (diff) | |
| download | coreboot-2847e1e71495158f1af02465fd6083674d767897.tar.xz | |
prog_loader: Associate TS_END_ROMSTAGE timestamp with postcar if exist
This patch adds timestamp for "end of romstage" with postcar if platform
has selected postcar as dedicated stage.
If postcar stage doesn't exist then "end of romstage" timestamp will get
call while starting of ramstage as exist today.
TEST=It's been observed that "end of romstage" timestamp doesn't appear
in "cbmem -t" log when ramstage is not getting executed. As part of this fix
"end of romstage" timestamp is showing in "cbmem -t" log on Intel platform
where POSTCAR is a dedicated stage.
Change-Id: I17fd89296354b66a5538f85737c79145232593d3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'util/intelmetool/intelmetool.c')
0 files changed, 0 insertions, 0 deletions