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authorNico Huber <nico.huber@secunet.com>2017-04-05 17:39:57 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2018-01-15 01:18:05 +0000
commit99b02a1d7c486d0b4083cbfdafe2a92de4975362 (patch)
treed4221e5772446d5158f642bec6cfbc20fe351aa6 /util/inteltool/Makefile
parent76a4f71e89722fd579daa559a1d24b3d710dbed6 (diff)
downloadcoreboot-99b02a1d7c486d0b4083cbfdafe2a92de4975362.tar.xz
inteltool: Support for nasty Primary to Sideband Bridge (P2SB)
The Primary to Sideband Bridge (P2SB) is the interface to Private Con- figuration Registers (PCR) including GPIO configuration. Of course, access is restricted to Intel partners and criminals, so the PCI device is hidden from the OS. Probably we only need to fetch the SBREG_BAR address and can hide the PCI device again after that. Change-Id: Ic121a09f021708aab82ae4b9d76d6c3c6fb884fa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'util/inteltool/Makefile')
-rw-r--r--util/inteltool/Makefile3
1 files changed, 2 insertions, 1 deletions
diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile
index 179bea9f85..d0f04899f0 100644
--- a/util/inteltool/Makefile
+++ b/util/inteltool/Makefile
@@ -27,7 +27,8 @@ LDFLAGS += -lpci -lz
CPPFLAGS += -I$(top)/src/commonlib/include
-OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o
+OBJS = inteltool.o pcr.o cpu.o gpio.o rootcmplx.o powermgt.o \
+ memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \
OS_ARCH = $(shell uname)
ifeq ($(OS_ARCH), Darwin)