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| author | Sven Schnelle <svens@stackframe.org> | 2011-10-30 13:30:36 +0100 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2011-10-30 13:37:16 +0100 |
| commit | 54a5aedec69bac62bf9bb5f65e431130507235fb (patch) | |
| tree | 6aaa5ac2568077f6d51c66bd8b980a2ac0e5cb47 /util/inteltool/gpio.c | |
| parent | 4c2bfb6256da0a4ffab94b3e810b9489e63a5c16 (diff) | |
| download | coreboot-54a5aedec69bac62bf9bb5f65e431130507235fb.tar.xz | |
inteltool: Add Intel i63xx I/O Controller Hub
Change-Id: Iaea7e4d1b206d43661ecb61d2ae517723fb8d008
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/356
Tested-by: build bot (Jenkins)
Diffstat (limited to 'util/inteltool/gpio.c')
| -rw-r--r-- | util/inteltool/gpio.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 6b56ec43a1..1d48a6800e 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -203,6 +203,24 @@ static const io_register_t ich10_gpio_registers[] = { { 0x7c, 4, "RESERVED" }, }; +static const io_register_t i631x_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x04, 4, "GP_IO_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "RESERVED" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "GPO_BLINK" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 4, "RESERVED" }, + { 0x24, 4, "RESERVED" }, + { 0x28, 4, "RESERVED" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "GPIO_USE_SEL2" }, + { 0x34, 4, "GP_IO_SEL2" }, + { 0x38, 4, "GP_LVL2" }, +}; + int print_gpios(struct pci_dev *sb) { int i, size; @@ -269,6 +287,13 @@ int print_gpios(struct pci_dev *sb) gpio_registers = ich0_gpio_registers; size = ARRAY_SIZE(ich0_gpio_registers); break; + + case PCI_DEVICE_ID_INTEL_I63XX: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = i631x_gpio_registers; + size = ARRAY_SIZE(i631x_gpio_registers); + break; + case PCI_DEVICE_ID_INTEL_82371XX: printf("This southbridge has GPIOs in the PM unit.\n"); return 1; |