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| author | Corey Osgood <corey.osgood@gmail.com> | 2010-08-17 08:33:44 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-08-17 08:33:44 +0000 |
| commit | f366ce05ef3eb95c6c9d84a97cde1a4026f22787 (patch) | |
| tree | 87733a7ba137fc9713fb96c2655ff6eef1a21e6f /util/inteltool/gpio.c | |
| parent | e7b7ae23e688fb883003aed42f614bcfa977894e (diff) | |
| download | coreboot-f366ce05ef3eb95c6c9d84a97cde1a4026f22787.tar.xz | |
Add support for the Intel NM10 (a variant of ICH7) and ICH8 southbridges.
Both are tested and appear to be working, however I'm not 100% clear
on if the NM10 has any other PCI IDs.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/inteltool/gpio.c')
| -rw-r--r-- | util/inteltool/gpio.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index a3b6e3d4a0..75658a9782 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -171,6 +171,7 @@ int print_gpios(struct pci_dev *sb) gpio_registers = ich9_gpio_registers; size = ARRAY_SIZE(ich9_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_ICH8: case PCI_DEVICE_ID_INTEL_ICH8M: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich8_gpio_registers; @@ -180,6 +181,7 @@ int print_gpios(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_NM10: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich7_gpio_registers; size = ARRAY_SIZE(ich7_gpio_registers); |