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author | Maciej Pijanka <maciej.pijanka@gmail.com> | 2009-09-30 17:05:46 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2009-09-30 17:05:46 +0000 |
commit | 90d17407d8eeda82a6f4ba2170e97f609e8cc71b (patch) | |
tree | c2a73173a22f4b0c7bba3a7f990f61a77116b958 /util/inteltool/gpio.c | |
parent | 2583dd209598249ca8380c3b58f90d15c9d55c2a (diff) | |
download | coreboot-90d17407d8eeda82a6f4ba2170e97f609e8cc71b.tar.xz |
Add initial inteltool support for Intel 440BX/440LX and 82371AB/EB/MB.
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/inteltool/gpio.c')
-rw-r--r-- | util/inteltool/gpio.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index fe8481e2fb..b4f11691dd 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -131,6 +131,9 @@ int print_gpios(struct pci_dev *sb) gpio_registers = ich0_gpio_registers; size = ARRAY_SIZE(ich0_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_82371XX: + printf("This southbridge has GPIOs in the PM unit.\n"); + return 1; case 0x1234: // Dummy for non-existent functionality printf("This southbridge does not have GPIOBASE.\n"); return 1; |