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| author | Maciej Pijanka <maciej.pijanka@gmail.com> | 2009-09-30 17:05:46 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2009-09-30 17:05:46 +0000 |
| commit | 90d17407d8eeda82a6f4ba2170e97f609e8cc71b (patch) | |
| tree | c2a73173a22f4b0c7bba3a7f990f61a77116b958 /util/inteltool/inteltool.h | |
| parent | 2583dd209598249ca8380c3b58f90d15c9d55c2a (diff) | |
| download | coreboot-90d17407d8eeda82a6f4ba2170e97f609e8cc71b.tar.xz | |
Add initial inteltool support for Intel 440BX/440LX and 82371AB/EB/MB.
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/inteltool/inteltool.h')
| -rw-r--r-- | util/inteltool/inteltool.h | 49 |
1 files changed, 29 insertions, 20 deletions
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 7f9c59d96b..b4757e53e8 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -32,27 +32,36 @@ #define INTELTOOL_VERSION "1.0" /* Tested chipsets: */ -#define PCI_VENDOR_ID_INTEL 0x8086 -#define PCI_DEVICE_ID_INTEL_ICH 0x2410 -#define PCI_DEVICE_ID_INTEL_ICH0 0x2420 -#define PCI_DEVICE_ID_INTEL_ICH2 0x2440 -#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 -#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc -#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 -#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 -#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 -#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd -#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 -#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_ICH 0x2410 +#define PCI_DEVICE_ID_INTEL_ICH0 0x2420 +#define PCI_DEVICE_ID_INTEL_ICH2 0x2440 +#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 +#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc +#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 +#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 +#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 +#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd +#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 +#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 -#define PCI_DEVICE_ID_INTEL_82810 0x7120 -#define PCI_DEVICE_ID_INTEL_82810DC 0x7122 -#define PCI_DEVICE_ID_INTEL_82845 0x1a30 -#define PCI_DEVICE_ID_INTEL_82945P 0x2770 -#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 -#define PCI_DEVICE_ID_INTEL_PM965 0x2a00 -#define PCI_DEVICE_ID_INTEL_82975X 0x277c -#define PCI_DEVICE_ID_INTEL_X58 0x3405 +#define PCI_DEVICE_ID_INTEL_82810 0x7120 +#define PCI_DEVICE_ID_INTEL_82810DC 0x7122 +#define PCI_DEVICE_ID_INTEL_82845 0x1a30 +#define PCI_DEVICE_ID_INTEL_82945P 0x2770 +#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 +#define PCI_DEVICE_ID_INTEL_PM965 0x2a00 +#define PCI_DEVICE_ID_INTEL_82975X 0x277c +#define PCI_DEVICE_ID_INTEL_X58 0x3405 + +#define PCI_DEVICE_ID_INTEL_82443LX 0x7180 + +/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */ +#define PCI_DEVICE_ID_INTEL_82443BX 0x7190 +#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192 + +/* 82371AB/EB/MB use the same device ID value. */ +#define PCI_DEVICE_ID_INTEL_82371XX 0x7110 #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) |