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| author | Felix Held <felix-coreboot@felixheld.de> | 2014-11-05 03:18:44 +0100 |
|---|---|---|
| committer | Mathias Krause <minipli@googlemail.com> | 2014-11-06 06:44:29 +0100 |
| commit | 0cc8f29316f6930406d70f71fc9409e295516b1e (patch) | |
| tree | 9a0e3599675a22638ecb00524ca4fdf0701cd856 /util/inteltool/inteltool.h | |
| parent | 5e1d34b19a6ad9c65f7c7833df3791707d5d9905 (diff) | |
| download | coreboot-0cc8f29316f6930406d70f71fc9409e295516b1e.tar.xz | |
inteltool: Add support for Sandy Bridge desktop processors
Change-Id: I5e68b89c30d5550e4bce5c3e4c7b0689c38756bc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/7337
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Mathias Krause <minipli@googlemail.com>
Diffstat (limited to 'util/inteltool/inteltool.h')
| -rw-r--r-- | util/inteltool/inteltool.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index cfee808eab..e031df316c 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -155,7 +155,8 @@ /* Intel starts counting these generations with the integration of the DRAM controller */ #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ -#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN 0x0104 /* Sandy Bridge */ +#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D 0x0100 /* Sandy Bridge (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M 0x0104 /* Sandy Bridge (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A 0x0150 /* Ivy Bridge */ #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B 0x0154 /* Ivy Bridge */ #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C 0x0158 /* Ivy Bridge */ |