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| author | Stefan Tauner <stefan.tauner@gmx.at> | 2013-06-20 18:05:06 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-06-23 23:36:03 +0200 |
| commit | dbc6fcd021759280c71b0e246c0ede34f4879bac (patch) | |
| tree | cec3448dd91f0ea075ce5f7d58b1809dc00925c8 /util/inteltool/memory.c | |
| parent | a390d779668146b60fdb89eaa709054d7811df7e (diff) | |
| download | coreboot-dbc6fcd021759280c71b0e246c0ede34f4879bac.tar.xz | |
inteltool: add initial support for Nehalem
Also, add pretty printing of Westmere's DMI registers (tested on my t410s
by staring at non-zero output values :)
Apparently Nehalem does not have a MEMBAR? But there are some
documented memory controller control registers in PCI configuration
space... left out for now.
The PCIEXBAR is not documented publicly AFAICT, but there is
a similar register on a device on bus 0xFF. phcoder might know more...
Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3505
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'util/inteltool/memory.c')
| -rw-r--r-- | util/inteltool/memory.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index be8b0cb3bd..18382e5416 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -246,7 +246,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */ - mch_registers = NULL; /* No public documentation */ + mch_registers = NULL; /* TODO: 322812 */ break; case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN: mch_registers = sandybridge_mch_registers; |