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| author | Corey Osgood <corey.osgood@gmail.com> | 2010-07-29 19:25:31 +0000 |
|---|---|---|
| committer | Corey Osgood <corey.osgood@gmail.com> | 2010-07-29 19:25:31 +0000 |
| commit | 23d98c768f0c0d53a71f77dd5f0ee83f01d66e16 (patch) | |
| tree | f0ea331087ea9228cb2a4c73600d78beaa90cabf /util/inteltool/memory.c | |
| parent | 9b3cf8ef0812fd21f438640543c7aa9d138ed69c (diff) | |
| download | coreboot-23d98c768f0c0d53a71f77dd5f0ee83f01d66e16.tar.xz | |
Add support for the Intel Atom D400/500- and N400-series integrated
northbridge. Also add support for the very similar Q963/965 northbridge.
Tested:
D510: confirmed working, with MCHBAR enable code
Q965: writes to bit 0 to enable MCHBAR access are ignored, all other functions work
Untested:
D410/D525/N400: should be the same northbridge
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/inteltool/memory.c')
| -rw-r--r-- | util/inteltool/memory.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 5c25dd0623..a076876526 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -47,6 +47,31 @@ int print_mchbar(struct pci_dev *nb) mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; + case PCI_DEVICE_ID_INTEL_Q965: + case PCI_DEVICE_ID_INTEL_ATOM_DXXX: + case PCI_DEVICE_ID_INTEL_ATOM_NXXX: + mchbar_phys = pci_read_long(nb, 0x48); + + /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads. + * If it isn't, try to set it. This may fail, because there is + * some bit that locks that bit, and isn't in the public + * datasheets. + */ + + if(!(mchbar_phys & 1)) + { + printf("Access to the MCHBAR is currently disabled, "\ + "attempting to enable.\n"); + mchbar_phys |= 0x1; + pci_write_long(nb, 0x48, mchbar_phys); + if(pci_read_long(nb, 0x48) & 1) + printf("Enabled successfully.\n"); + else + printf("Enable FAILED!\n"); + } + mchbar_phys &= 0xfffffffe; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; case PCI_DEVICE_ID_INTEL_82443LX: case PCI_DEVICE_ID_INTEL_82443BX: case PCI_DEVICE_ID_INTEL_82810: |