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authorStefan Tauner <stefan.tauner@gmx.at>2016-05-05 17:29:39 +0200
committerMartin Roth <martinroth@google.com>2016-05-13 16:58:56 +0200
commit572f07497104e1f9c4e1ed0fd01850a9e2a4803f (patch)
tree0d9aba06f48bfd30ae98e67b10b93943215392fc /util/inteltool/memory.c
parentc3ee3f6d7efaeba91be2a04e694577f061c3668a (diff)
downloadcoreboot-572f07497104e1f9c4e1ed0fd01850a9e2a4803f.tar.xz
inteltool: update documentation
- manpage - usage message - new warning message if -S is used on an unsupported chipset Change-Id: I1acaa5f4232b65244ec00fd22ec7460d9cc387f1 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/14624 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'util/inteltool/memory.c')
-rw-r--r--util/inteltool/memory.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index 5f047297ed..686c1e7ae1 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -253,6 +253,8 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1);
dump_timings ();
+ if (dump_spd_file != NULL)
+ printf("\nCreating a memory timings file is not supported on this chipset.\n");
break;
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
@@ -263,6 +265,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
ivybridge_dump_timings(dump_spd_file);
break;
+ default:
+ if (dump_spd_file != NULL)
+ printf("\nCreating a memory timings file is not supported on this chipset.\n");
}
unmap_physical((void *)mchbar, size);
return 0;