inteltool: new definitions and cleanup

 - Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[].
 - Refine some names and macros.
 - Clean up some whitespace errors.

 - Add IDs and names of 5, 6 and 7 Series southbridges and the three
   latest Core CPU families with integrated memory controllers but do
   not implement any pretty printing routines for them yet.

   The first generation Core family is already supported, although it
   was wrongly named after the PCH and used the wrong ID. Also, the BAR
   values have been mangled to 32b instead of 64b. Both errors have been
   fixed and most basic support for the other two generations was added.

Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1574
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

1 files changed, 42 insertions, 33 deletions

diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index a7429a0202..e454f44b16 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -94,22 +94,22 @@ int print_epbar(struct pci_dev *nb)
 	case PCI_DEVICE_ID_INTEL_82975X:
 		epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
 		break;
- 	case PCI_DEVICE_ID_INTEL_PM965:
- 	case PCI_DEVICE_ID_INTEL_Q965:
- 	case PCI_DEVICE_ID_INTEL_82Q35:
- 	case PCI_DEVICE_ID_INTEL_82G33:
- 	case PCI_DEVICE_ID_INTEL_82Q33:
-	case PCI_DEVICE_ID_INTEL_X44:
+	case PCI_DEVICE_ID_INTEL_82965PM:
+	case PCI_DEVICE_ID_INTEL_82Q965:
+	case PCI_DEVICE_ID_INTEL_82Q35:
+	case PCI_DEVICE_ID_INTEL_82G33:
+	case PCI_DEVICE_ID_INTEL_82Q33:
+	case PCI_DEVICE_ID_INTEL_82X38:
 	case PCI_DEVICE_ID_INTEL_32X0:
-	case PCI_DEVICE_ID_INTEL_GS45:
+	case PCI_DEVICE_ID_INTEL_82X4X:
 	case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
 	case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
- 		epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
- 		epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
- 		break;
+		epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
+		epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
+		break;
 	case PCI_DEVICE_ID_INTEL_82810:
-	case PCI_DEVICE_ID_INTEL_82810DC:
-	case PCI_DEVICE_ID_INTEL_82810E_MC:
+	case PCI_DEVICE_ID_INTEL_82810_DC:
+	case PCI_DEVICE_ID_INTEL_82810E_DC:
 	case PCI_DEVICE_ID_INTEL_82830M:
 	case PCI_DEVICE_ID_INTEL_82865:
 		printf("This northbridge does not have EPBAR.\n");
@@ -156,32 +156,41 @@ int print_dmibar(struct pci_dev *nb)
 	case PCI_DEVICE_ID_INTEL_82975X:
 		dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
 		break;
-	case PCI_DEVICE_ID_INTEL_PM965:
-	case PCI_DEVICE_ID_INTEL_Q965:
+	case PCI_DEVICE_ID_INTEL_82965PM:
+	case PCI_DEVICE_ID_INTEL_82Q965:
 	case PCI_DEVICE_ID_INTEL_82Q35:
 	case PCI_DEVICE_ID_INTEL_82G33:
 	case PCI_DEVICE_ID_INTEL_82Q33:
-	case PCI_DEVICE_ID_INTEL_X44:
+	case PCI_DEVICE_ID_INTEL_82X38:
 	case PCI_DEVICE_ID_INTEL_32X0:
-	case PCI_DEVICE_ID_INTEL_GS45:
+	case PCI_DEVICE_ID_INTEL_82X4X:
 	case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
 	case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
 		dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
 		dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
 		break;
 	case PCI_DEVICE_ID_INTEL_82810:
-	case PCI_DEVICE_ID_INTEL_82810DC:
-	case PCI_DEVICE_ID_INTEL_82810E_MC:
+	case PCI_DEVICE_ID_INTEL_82810_DC:
+	case PCI_DEVICE_ID_INTEL_82810E_DC:
 	case PCI_DEVICE_ID_INTEL_82865:
 		printf("This northbridge does not have DMIBAR.\n");
 		return 1;
-	case PCI_DEVICE_ID_INTEL_X58:
+	case PCI_DEVICE_ID_INTEL_82X58:
 		dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
 		break;
-	case PCI_DEVICE_ID_INTEL_HM65E:
-		dmibar_phys = pci_read_long(nb, 0x68) & 0xfffff000;
+	case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
+		dmibar_phys = pci_read_long(nb, 0x68);
+		dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
+		dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */
+		dmi_registers = NULL; /* No public documentation */
+		break;
+	case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
 		dmi_registers = sandybridge_dmi_registers;
 		size = ARRAY_SIZE(sandybridge_dmi_registers);
+	case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */
+		dmibar_phys = pci_read_long(nb, 0x68);
+		dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
+		dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
 		break;
 	default:
 		printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
@@ -251,22 +260,22 @@ int print_pciexbar(struct pci_dev *nb)
 	case PCI_DEVICE_ID_INTEL_82975X:
 		pciexbar_reg = pci_read_long(nb, 0x48);
 		break;
- 	case PCI_DEVICE_ID_INTEL_PM965:
-	case PCI_DEVICE_ID_INTEL_Q965:
- 	case PCI_DEVICE_ID_INTEL_82Q35:
- 	case PCI_DEVICE_ID_INTEL_82G33:
- 	case PCI_DEVICE_ID_INTEL_82Q33:
-	case PCI_DEVICE_ID_INTEL_X44:
+	case PCI_DEVICE_ID_INTEL_82965PM:
+	case PCI_DEVICE_ID_INTEL_82Q965:
+	case PCI_DEVICE_ID_INTEL_82Q35:
+	case PCI_DEVICE_ID_INTEL_82G33:
+	case PCI_DEVICE_ID_INTEL_82Q33:
+	case PCI_DEVICE_ID_INTEL_82X38:
 	case PCI_DEVICE_ID_INTEL_32X0:
-	case PCI_DEVICE_ID_INTEL_GS45:
+	case PCI_DEVICE_ID_INTEL_82X4X:
 	case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
 	case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
- 		pciexbar_reg = pci_read_long(nb, 0x60);
- 		pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
- 		break;
+		pciexbar_reg = pci_read_long(nb, 0x60);
+		pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
+		break;
 	case PCI_DEVICE_ID_INTEL_82810:
-	case PCI_DEVICE_ID_INTEL_82810DC:
-	case PCI_DEVICE_ID_INTEL_82810E_MC:
+	case PCI_DEVICE_ID_INTEL_82810_DC:
+	case PCI_DEVICE_ID_INTEL_82810E_DC:
 	case PCI_DEVICE_ID_INTEL_82865:
 		printf("Error: This northbridge does not have PCIEXBAR.\n");
 		return 1;