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author | Idwer Vollering <vidwer@gmail.com> | 2010-12-17 22:34:58 +0000 |
---|---|---|
committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-17 22:34:58 +0000 |
commit | 312fc96874ff2b3fd1a839b72dd10edb1b8937b8 (patch) | |
tree | a73f2971e0d8dbf9927f3ab5e933acfc0a5a3d30 /util/inteltool/pcie.c | |
parent | 397ff6815f48182e9f05372aefcad55950d2dc36 (diff) | |
download | coreboot-312fc96874ff2b3fd1a839b72dd10edb1b8937b8.tar.xz |
inteltool: Model 0xf2x, ICH5, i865 support.
Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM
registers on ICH5. Add ICH5 and i865 to the supported chips list.
Enable the dumping of BAR6 on i865.
Sample output:
Disabling memory access:
$ sudo setpci -s 6.0 0x04.b=0x0
$ sudo ./inteltool -m | head -n 9
Intel CPU: Processor Type: 0, Family f, Model 2, Stepping 7
Intel Northbridge: 8086:2570 (i865)
Intel Southbridge: 8086:24d0 (ICH5)
============= MCHBAR ============
Access to BAR6 is currently disabled, attempting to enable.
Enabled successfully.
BAR6 = 0xfecf0000 (MEM)
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/inteltool/pcie.c')
-rw-r--r-- | util/inteltool/pcie.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 2c0f6a43ea..1ca57b6c05 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -55,7 +55,8 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82810DC: case PCI_DEVICE_ID_INTEL_82810E_MC: case PCI_DEVICE_ID_INTEL_82830M: - printf("This northbrigde does not have EPBAR.\n"); + case PCI_DEVICE_ID_INTEL_82865: + printf("This northbridge does not have EPBAR.\n"); return 1; default: printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n"); @@ -112,7 +113,8 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82810: case PCI_DEVICE_ID_INTEL_82810DC: case PCI_DEVICE_ID_INTEL_82810E_MC: - printf("This northbrigde does not have DMIBAR.\n"); + case PCI_DEVICE_ID_INTEL_82865: + printf("This northbridge does not have DMIBAR.\n"); return 1; case PCI_DEVICE_ID_INTEL_X58: dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; @@ -174,7 +176,8 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82810: case PCI_DEVICE_ID_INTEL_82810DC: case PCI_DEVICE_ID_INTEL_82810E_MC: - printf("Error: This northbrigde does not have PCIEXBAR.\n"); + case PCI_DEVICE_ID_INTEL_82865: + printf("Error: This northbridge does not have PCIEXBAR.\n"); return 1; default: printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n"); @@ -245,5 +248,3 @@ int print_pciexbar(struct pci_dev *nb) return 0; } - - |