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| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2020-07-16 22:02:43 +0300 |
|---|---|---|
| committer | David Hendricks <david.hendricks@gmail.com> | 2020-07-21 16:39:14 +0000 |
| commit | ec0551c6b061d0bef1f9a8ec3027f7eabd088cbb (patch) | |
| tree | 7ccd647ff03f766eeb35e70b01061e55df539c18 /util/inteltool/pcie.c | |
| parent | 3c7888bf293ad6c5d879dd0ef1ddc1a6bad7470c (diff) | |
| download | coreboot-ec0551c6b061d0bef1f9a8ec3027f7eabd088cbb.tar.xz | |
util/inteltool: add missing L0 and L1 pads for Lewisburg
The description for L0 and L1 was missed in the datasheet, however,
configuration registers for these pads are present. In addition, the
chipset contains the "GPP_L0/CSME_INTR_IN" and "GPP_L1/CSME_INTR_OUT"
pads in a circuit diagram. Use all available information to add a
description for the missed pads.
Change-Id: I7a0488c26b3df9de1adc037d94ae290837d65dd8
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40044
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/inteltool/pcie.c')
0 files changed, 0 insertions, 0 deletions