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| author | Felix Held <felix-coreboot@felixheld.de> | 2014-11-09 00:11:28 +0100 |
|---|---|---|
| committer | Mathias Krause <minipli@googlemail.com> | 2014-11-09 21:11:27 +0100 |
| commit | fac95e3bfe7d32ee1b9a89afd8a76c2c41c6b695 (patch) | |
| tree | c7884e7ed49adf4891707084deec06e1d74ed498 /util/inteltool/pcie.c | |
| parent | a6aecc41eff1fd26e6399f93f143951b4d16417b (diff) | |
| download | coreboot-fac95e3bfe7d32ee1b9a89afd8a76c2c41c6b695.tar.xz | |
inteltool: add more hardware IDs and PCIEXBAR/PXPEPBAR read support
Add IDs of some SNB and Haswell chips; use more descriptive names.
Add PCIEXBAR and PXPEPBAR read support for SNB/IVB/Haswell.
Change-Id: I16753bf90061fc2065b813b1c2169e7b7bcc89e8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/7360
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
Diffstat (limited to 'util/inteltool/pcie.c')
| -rw-r--r-- | util/inteltool/pcie.c | 32 |
1 files changed, 28 insertions, 4 deletions
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 549ef4b678..6fa94e9ad8 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -205,6 +205,16 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; @@ -296,12 +306,16 @@ int print_dmibar(struct pci_dev *nb) break; case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: dmi_registers = sandybridge_dmi_registers; size = ARRAY_SIZE(sandybridge_dmi_registers); - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: /* pretty printing not implemented yet */ - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B: - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C: - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: /* pretty printing not implemented yet */ + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: dmibar_phys = pci_read_long(nb, 0x68); dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ @@ -393,6 +407,16 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; |