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| author | Nikolay Petukhov <nikolay.petukhov@gmail.com> | 2008-05-17 01:08:58 +0000 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2008-05-17 01:08:58 +0000 |
| commit | ce1fb9d4e96d6553ddee1b5bda9a58148c81057c (patch) | |
| tree | a729b5c04c208dd2a6013c296dad48535d6a080e /util/inteltool | |
| parent | fb047a6a54ffd872a4059d04a3f2a8b59ae9ab29 (diff) | |
| download | coreboot-ce1fb9d4e96d6553ddee1b5bda9a58148c81057c.tar.xz | |
flashrom: Support Pm49FL004/2 Block Locking Registers
The PMC chips understand both LPC and FWH flash commands. When in FWH mode
(MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d on 5536 boards) the Block
Locking Registers by default lock the flash chip for write and erase - in
addition to any chipset write protection.
This patch adds unlock operations before Pm49FL004/2 write and erase, and
it includes an svn mv pm49fl004.c pm49fl00x.c
Thanks go to Nikolay for this patch.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Bari Ari <bari@onelabs.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/inteltool')
0 files changed, 0 insertions, 0 deletions