inteltool: add initial support for Nehalem

Also, add pretty printing of Westmere's DMI registers (tested on my t410s
by staring at non-zero output values :)

Apparently Nehalem does not have a MEMBAR? But there are some
documented memory controller control registers in PCI configuration
space... left out for now.

The PCIEXBAR is not documented publicly AFAICT, but there is
a similar register on a device on bus 0xFF. phcoder might know more...

Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3505
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

4 files changed, 54 insertions, 2 deletions

diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index a4edca96df..5cd964a34d 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -71,6 +71,7 @@ static const struct {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" },
 	/* Host bridges /DRAM controllers integrated in CPUs */
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN, "0th generation (Nehalem family) Core Processor" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN, "2nd generation (Sandy Bridge family) Core Processor" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN, "3rd generation (Ivy Bridge family) Core Processor" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index dc5c832e6e..88008e4e17 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -151,6 +151,7 @@
 #define PCI_DEVICE_ID_INTEL_82371XX		0x7110
 
 /* Intel starts counting these generations with the integration of the DRAM controller */
+#define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN	0xd132 /* Nehalem */
 #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN	0x0044 /* Westmere */
 #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN	0x0104 /* Sandy Bridge */
 #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN	0x0154 /* Ivy Bridge */
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index be8b0cb3bd..18382e5416 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -246,7 +246,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
 		mchbar_phys = pci_read_long(nb, 0x48);
 		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
 		mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */
-		mch_registers = NULL; /* No public documentation */
+		mch_registers = NULL; /* TODO: 322812 */
 		break;
 	case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
 		mch_registers = sandybridge_mch_registers;
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 8c95257e52..cafd34ab37 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -23,6 +23,49 @@
 #include <inttypes.h>
 #include "inteltool.h"
 
+/* 320766 */
+static const io_register_t nehalem_dmi_registers[] = {
+	{ 0x00, 4, "DMIVCH" },		// DMI Virtual Channel Capability Header
+	{ 0x04, 4, "DMIVCCAP1" },	// DMI Port VC Capability Register 1
+	{ 0x08, 4, "DMIVCCAP2" },	// DMI Port VC Capability Register 2
+	{ 0x0C, 4, "DMIVCCTL" },	// DMI Port VC Control
+	{ 0x10, 4, "DMIVC0RCAP" },	// DMI VC0 Resource Capability
+	{ 0x14, 4, "DMIVC0RCTL" },	// DMI VC0 Resource Control
+/*	{ 0x18, 2, "RSVD" }, // Reserved */
+	{ 0x1A, 2, "DMIVC0RSTS" },	// DMI VC0 Resource Status
+	{ 0x1C, 4, "DMIVC1RCAP" },	// DMI VC1 Resource Capability
+	{ 0x20, 4, "DMIVC1RCTL" },	// DMI VC1 Resource Control
+/*	{ 0x24, 2, "RSVD" }, // Reserved */
+	{ 0x26, 2, "DMIVC1RSTS" },	// DMI VC1 Resource Status
+/*	... - Reserved */
+	{ 0x84, 4, "DMILCAP" },		// DMI Link Capabilities
+	{ 0x88, 2, "DMILCTL" },		// DMI Link Control
+	{ 0x8A, 2, "DMILSTS" },		// DMI Link Status
+/*	... - Reserved */
+};
+
+/* 322812 */
+static const io_register_t westmere_dmi_registers[] = {
+	{ 0x00, 4, "DMIVCECH" },	// DMI Virtual Channel Enhanced Capability
+	{ 0x04, 4, "DMIPVCCAP1" },	// DMI Port VC Capability Register 1
+	{ 0x08, 4, "DMIPVCCAP2" },	// DMI Port VC Capability Register 2
+	{ 0x0C, 2, "DMIPVCCTL" },	// DMI Port VC Control
+/*	{ 0x0E, 2, "RSVD" }, // Reserved */
+	{ 0x10, 4, "DMIVC0RCAP" },	// DMI VC0 Resource Capability
+	{ 0x14, 4, "DMIVC0RCTL" },	// DMI VC0 Resource Control
+/*	{ 0x18, 2, "RSVD" }, // Reserved */
+	{ 0x1A, 2, "DMIVC0RSTS" },	// DMI VC0 Resource Status
+	{ 0x1C, 4, "DMIVC1RCAP" },	// DMI VC1 Resource Capability
+	{ 0x20, 4, "DMIVC1RCTL1" },	// DMI VC1 Resource Control
+/*	{ 0x24, 2, "RSVD" },	// Reserved */
+	{ 0x26, 2, "DMIC1RSTS" },	// DMI VC1 Resource Status
+/*	... - Reserved */
+	{ 0x84, 4, "DMILCAP" },		// DMI Link Capabilities
+	{ 0x88, 2, "DMILCTL" },		// DMI Link Control
+	{ 0x8A, 2, "DMILSTS" },		// DMI Link Status
+/*	... - Reserved */
+};
+
 static const io_register_t sandybridge_dmi_registers[] = {
 	{ 0x00, 4, "DMI VCECH" }, // DMI Virtual Channel Enhanced Capability
 	{ 0x04, 4, "DMI PVCCAP1" }, // DMI Port VC Capability Register 1
@@ -180,11 +223,18 @@ int print_dmibar(struct pci_dev *nb)
 	case PCI_DEVICE_ID_INTEL_82X58:
 		dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
 		break;
+	case PCI_DEVICE_ID_INTEL_CORE_0TH_GEN:
+		/* DMIBAR is called DMIRCBAR in Nehalem */
+		dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; /* 31:12 */
+		dmi_registers = nehalem_dmi_registers;
+		size = ARRAY_SIZE(nehalem_dmi_registers);
+		break;
 	case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
 		dmibar_phys = pci_read_long(nb, 0x68);
 		dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
 		dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */
-		dmi_registers = NULL; /* No public documentation */
+		dmi_registers = westmere_dmi_registers;
+		size = ARRAY_SIZE(westmere_dmi_registers);
 		break;
 	case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
 		dmi_registers = sandybridge_dmi_registers;