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authorElyes HAOUAS <ehaouas@noos.fr>2020-02-16 16:22:52 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-02-17 20:11:24 +0000
commit6dc9d0352e9c2dafb46c8c827d07cfdba2d744dd (patch)
tree54f4bdf90f1e9ecc9b377b084bfb44396ee0693a /util/inteltool
parentc7a3152273ef3179e3ad5f66f53c4a9d2aa39c8e (diff)
downloadcoreboot-6dc9d0352e9c2dafb46c8c827d07cfdba2d744dd.tar.xz
treewide: capitalize 'BIOS'
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'util/inteltool')
-rw-r--r--util/inteltool/inteltool.82
-rw-r--r--util/inteltool/spi.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8
index 86a76bdc9a..01e3cfd7f2 100644
--- a/util/inteltool/inteltool.8
+++ b/util/inteltool/inteltool.8
@@ -32,7 +32,7 @@ Show only GPIO register differences from hardware defaults.
Dump I/O Controller Hub (ICH) southbridge RCBA registers.
.TP
.B "\-s, \-\-spi"
-Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control.
+Dump I/O Controller Hub (ICH) southbridge SPI registers and BIOS control.
.TP
.B "\-f, \-\-gfx"
.RB "Dump graphics registers. " \
diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c
index 22ba3d42f2..e8289acaf3 100644
--- a/util/inteltool/spi.c
+++ b/util/inteltool/spi.c
@@ -22,7 +22,7 @@ static const io_register_t pch_bios_cntl_registers[] = {
{ 0x1, 1, "BLE - lock enable" },
{ 0x2, 2, "SPI Read configuration" },
{ 0x4, 1, "TopSwapStatus" },
- { 0x5, 1, "SMM Bios Write Protect Disable" },
+ { 0x5, 1, "SMM BIOS Write Protect Disable" },
{ 0x6, 2, "reserved" },
};