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| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2020-07-14 21:44:47 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-26 21:47:22 +0000 |
| commit | e9b0db388cdad6fb817487a35e89cce8348332b7 (patch) | |
| tree | b87bae6d464736c057482f2b5e8245ae5c1dc804 /util/inteltool | |
| parent | 148f8397d2793a465623877d311733eb82e4fe69 (diff) | |
| download | coreboot-e9b0db388cdad6fb817487a35e89cce8348332b7.tar.xz | |
mb/intel/cedarisland/Makefile: Add missing ramstage.c
Fixes a bug in Makefile.inc, which did not allow building ROM image
with ramstage.c from motherboard configuration.
Change-Id: I70d8a2e1f53e2fa56d514361116a55f175407753
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43457
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/inteltool')
0 files changed, 0 insertions, 0 deletions