inteltool: Add support for H65 Express chipset

Added few MCH and DMI registers for H65E.
Description of them can be found at
"2nd Generation Intel Core Processors
Family datasheet"

Change-Id: If4fee35bb5a09b04ea0684be9cbd3c1e9084b934
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1258
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

4 files changed, 171 insertions, 6 deletions

diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index ef354f2b1b..56bbc4a458 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -54,6 +54,7 @@ static const struct {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM65E, "HM65 Express" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 22ebc3d346..aa8a292a5b 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -102,6 +102,8 @@
 /* 82371AB/EB/MB use the same device ID value. */
 #define PCI_DEVICE_ID_INTEL_82371XX		0x7110
 
+#define PCI_DEVICE_ID_INTEL_HM65E		0x0104
+
 #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
 
 #if !defined(__DARWIN__) && !defined(__FreeBSD__)
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index 18300ac445..d66ee4884d 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -23,6 +23,47 @@
 #include <inttypes.h>
 #include "inteltool.h"
 
+static const io_register_t sandybridge_mch_registers[] = {
+/* Channel 0 */
+	{ 0x4000, 4, "TC_DBP_C0" }, // Timing of DDR Bin Parameters
+	{ 0x4004, 4, "TC_RAP_C0" }, // Timing of DDR Regular Access Parameters
+	{ 0x4028, 4, "SC_IO_LATENCY_C0" }, // IO Latency Configuration
+	{ 0x42A4, 4, "TC_SRFTP_C0" }, // Self-Refresh Timing Parameters
+	{ 0x40B0, 4, "PM_PDWN_config_C0" }, // Power-down Configuration
+	{ 0x4294, 4, "TC_RFP_C0" }, // Refresh Parameters
+	{ 0x4298, 4, "TC_RFTP_C0" }, // Refresh Timing Parameters
+/* Channel 1 */
+	{ 0x4400, 4, "TC_DBP_C1" }, // Timing of DDR Bin Parameters
+	{ 0x4404, 4, "TC_RAP_C1" }, // Timing of DDR Regular Access Parameters
+	{ 0x4428, 4, "SC_IO_LATENCY_C1" }, // IO Latency Configuration
+	{ 0x46A4, 4, "TC_SRFTP_C1" }, // Self-Refresh Timing Parameters
+	{ 0x44B0, 4, "PM_PDWN_config_C1" }, // Power-down Configuration
+	{ 0x4694, 4, "TC_RFP_C1" }, // Refresh Parameters
+	{ 0x4698, 4, "TC_RFTP_C1" }, // Refresh Timing Parameters
+/* Integrated Memory Peripheral Hub (IMPH) */
+	{ 0x740C, 4, "CRDTCTL3" }, // Credit Control 3
+/* Common Registers */
+	{ 0x5000, 4, "MAD_CHNL" }, // Address decoder Channel Configuration
+	{ 0x5004, 4, "MAD_DIMM_ch0" }, // Address Decode Channel 0
+	{ 0x5008, 4, "MAD_DIMM_ch1" }, // Address Decode Channel 1
+	{ 0x5060, 4, "PM_SREF_config" }, // Self Refresh Configuration
+/* MMIO Registers Broadcast Group */
+	{ 0x4CB0, 4, "PM_PDWN_config" }, // Power-down Configuration
+	{ 0x4F84, 4, "PM_CMD_PWR" }, // Power Management Command Power
+	{ 0x4F88, 4, "PM_BW_LIMIT_config" }, // BW Limit Configuration
+	{ 0x4F8C, 4, "RESERVED" }, // Reserved, default value - 0xFF1D1519
+/* PCU MCHBAR Registers */
+	{ 0x5880, 4, "MEM_TRML_ESTIMATION_CONFIG" }, // Memory Thermal Estimation Configuration
+	{ 0x5884, 4, "RESERVED" }, // Reserved
+	{ 0x5888, 4, "MEM_TRML_THRESHOLDS_CONFIG" }, // Memory Thermal Thresholds Configuration
+	{ 0x58A0, 4, "MEM_TRML_STATUS_REPORT" }, // Memory Thermal Status Report
+	{ 0x58A4, 4, "MEM_TRML_TEMPERATURE_REPORT" }, // Memory Thermal Temperature Report
+	{ 0x58A8, 4, "MEM_TRML_INTERRUPT" }, // Memory Thermal Interrupt
+	{ 0x5948, 4, "GT_PERF_STATUS" }, // GT Performance Status
+	{ 0x5998, 4, "RP_STATE_CAP" }, // RP State Capability
+	{ 0x5D10, 8, "SSKPD" }, // Sticky Scratchpad Data
+};
+
 /*
  * (G)MCH MMIO Config Space
  */
@@ -31,6 +72,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
 	int i, size = (16 * 1024);
 	volatile uint8_t *mchbar;
 	uint64_t mchbar_phys;
+	const io_register_t *mch_registers = NULL;
 	struct pci_dev *nb_device6; /* "overflow device" on i865 */
 	uint16_t pcicmd6;
 
@@ -115,6 +157,11 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
 		mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
 		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
  		break;
+	case PCI_DEVICE_ID_INTEL_HM65E:
+		mchbar_phys = pci_read_long(nb, 0x48) & 0xffff8000;
+		mch_registers = sandybridge_mch_registers;
+		size = ARRAY_SIZE(sandybridge_mch_registers);
+		break;
 	default:
 		printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
 		return 1;
@@ -135,9 +182,40 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
 	else
 		printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
 
-	for (i = 0; i < size; i += 4) {
-		if (*(uint32_t *)(mchbar + i))
-			printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i));
+	if (mch_registers != NULL) {
+		for (i = 0; i < size; i++) {
+			switch (mch_registers[i].size) {
+				case 8:
+					printf("mchbase+0x%04x: 0x%08lx (%s)\n",
+						mch_registers[i].addr,
+						*(uint64_t *)(mchbar+mch_registers[i].addr),
+						mch_registers[i].name);
+					break;
+				case 4:
+					printf("mchbase+0x%04x: 0x%08x (%s)\n",
+						mch_registers[i].addr,
+						*(uint32_t *)(mchbar+mch_registers[i].addr),
+						mch_registers[i].name);
+					break;
+				case 2:
+					printf("mchbase+0x%04x: 0x%04x     (%s)\n",
+						mch_registers[i].addr,
+						*(uint16_t *)(mchbar+mch_registers[i].addr),
+						mch_registers[i].name);
+					break;
+				case 1:
+					printf("mchbase+0x%04x: 0x%02x       (%s)\n",
+						mch_registers[i].addr,
+						*(uint8_t *)(mchbar+mch_registers[i].addr),
+						mch_registers[i].name);
+					break;
+			}
+		}
+	} else {
+		for (i = 0; i < size; i += 4) {
+			if (*(uint32_t *)(mchbar + i))
+				printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i));
+		}
 	}
 
 	unmap_physical((void *)mchbar, size);
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index ea23835425..a7429a0202 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -2,6 +2,7 @@
  * inteltool - dump all registers on an Intel CPU + chipset based system.
  *
  * Copyright (C) 2008-2010 by coresystems GmbH
+ * Copyright (C) 2012 Anton Kochkov
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,6 +23,58 @@
 #include <inttypes.h>
 #include "inteltool.h"
 
+static const io_register_t sandybridge_dmi_registers[] = {
+	{ 0x00, 4, "DMI VCECH" }, // DMI Virtual Channel Enhanced Capability
+	{ 0x04, 4, "DMI PVCCAP1" }, // DMI Port VC Capability Register 1
+	{ 0x08, 4, "DMI PVVAP2" }, // DMI Port VC Capability Register 2
+	{ 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control
+/*	{ 0x0E, 2, "RSVD" }, // Reserved */
+	{ 0x10, 4, "DMI VC0RCAP" }, // DMI VC0 Resource Capability
+	{ 0x14, 4, "DMI VC0RCTL" }, // DMI VC0 Resource Control
+/*	{ 0x18, 2, "RSVD" }, // Reserved */
+	{ 0x1A, 2, "DMI VC0RSTS" }, // DMI VC0 Resource Status
+	{ 0x1C, 4, "DMI VC1RCAP" }, // DMI VC1 Resource Capability
+	{ 0x20, 4, "DMI VC1RCTL" }, // DMI VC1 Resource Control
+/*	{ 0x24, 2, "RSVD" }, // Reserved */
+	{ 0x26, 2, "DMI VC1RSTS" }, // DMI VC1 Resource Status
+	{ 0x28, 4, "DMI VCPRCAP" }, // DMI VCp Resource Capability
+	{ 0x2C, 4, "DMI VCPRCTL" }, // DMI VCp Resource Control
+/*	{ 0x30, 2, "RSVD" }, // Reserved */
+	{ 0x32, 2, "DMI VCPRSTS" }, // DMI VCp Resource Status
+	{ 0x34, 4, "DMI VCMRCAP" }, // DMI VCm Resource Capability
+	{ 0x38, 4, "DMI VCMRCTL" }, // DMI VCm Resource Control
+/*	{ 0x3C, 2, "RSVD" }, // Reserved */
+	{ 0x3E, 2, "DMI VCMRSTS" }, // DMI VCm Resource Status
+/*	{ 0x40, 4, "RSVD" }, // Reserved */
+	{ 0x44, 4, "DMI ESC" }, // DMI Element Self Description
+/*	{ 0x48, 8, "RSVD" }, // Reserved */
+	{ 0x50, 4, "DMI LE1D" }, // DMI Link Entry 1 Description
+/*	{ 0x54, 4, "RSVD" }, // Reserved */
+	{ 0x58, 4, "DMI LE1A" }, // DMI Link Entry 1 Address
+	{ 0x5C, 4, "DMI LUE1A" }, // DMI Link Upper Entry 1 Address
+	{ 0x60, 4, "DMI LE2D" }, // DMI Link Entry 2 Description
+/*	{ 0x64, 4, "RSVD" }, // Reserved */
+	{ 0x68, 4, "DMI LE2A" }, // DMI Link Entry 2 Address
+/*	{ 0x6C, 4, "RSVD" }, // Reserved
+	{ 0x70, 8, "RSVD" }, // Reserved
+	{ 0x78, 8, "RSVD" }, // Reserved
+	{ 0x80, 4, "RSVD" }, // Reserved */
+	{ 0x84, 4, "LCAP" }, // Link Capabilities
+	{ 0x88, 2, "LCTL" }, // Link Control
+	{ 0x8A, 2, "LSTS" }, // Link Status
+/*	{ 0x8C, 4, "RSVD" }, // Reserved
+	{ 0x90, 4, "RSVD" }, // Reserved
+	{ 0x94, 4, "RSVD" }, // Reserved */
+	{ 0x98, 2, "LCTL2" }, // Link Control 2
+	{ 0x9A, 2, "LSTS2" }, // Link Status 2
+/*	... - Reserved */
+	{ 0xBC0, 4, "AFE_BMUF0" }, // AFE BMU Configuration Function 0
+	{ 0xBC4, 4, "RSVD" }, // Reserved
+	{ 0xBC8, 4, "RSVD" }, // Reserved
+	{ 0xBCC, 4, "AFE_BMUT0" }, // AFE BMU Configuration Test 0
+/*	... - Reserved */
+};
+
 /*
  * Egress Port Root Complex MMIO configuration space
  */
@@ -91,6 +144,7 @@ int print_dmibar(struct pci_dev *nb)
 	int i, size = (4 * 1024);
 	volatile uint8_t *dmibar;
 	uint64_t dmibar_phys;
+	const io_register_t *dmi_registers = NULL;
 
 	printf("\n============= DMIBAR ============\n\n");
 
@@ -124,6 +178,11 @@ int print_dmibar(struct pci_dev *nb)
 	case PCI_DEVICE_ID_INTEL_X58:
 		dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
 		break;
+	case PCI_DEVICE_ID_INTEL_HM65E:
+		dmibar_phys = pci_read_long(nb, 0x68) & 0xfffff000;
+		dmi_registers = sandybridge_dmi_registers;
+		size = ARRAY_SIZE(sandybridge_dmi_registers);
+		break;
 	default:
 		printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
 		return 1;
@@ -137,9 +196,34 @@ int print_dmibar(struct pci_dev *nb)
 	}
 
 	printf("DMIBAR = 0x%08" PRIx64 " (MEM)\n\n", dmibar_phys);
-	for (i = 0; i < size; i += 4) {
-		if (*(uint32_t *)(dmibar + i))
-			printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
+	if (dmi_registers != NULL) {
+		for (i = 0; i < size; i++) {
+			switch (dmi_registers[i].size) {
+				case 4:
+					printf("dmibase+0x%04x: 0x%08x (%s)\n",
+						dmi_registers[i].addr,
+						*(uint32_t *)(dmibar+dmi_registers[i].addr),
+						dmi_registers[i].name);
+					break;
+				case 2:
+					printf("dmibase+0x%04x: 0x%04x     (%s)\n",
+						dmi_registers[i].addr,
+						*(uint16_t *)(dmibar+dmi_registers[i].addr),
+						dmi_registers[i].name);
+					break;
+				case 1:
+					printf("dmibase+0x%04x: 0x%02x       (%s)\n",
+						dmi_registers[i].addr,
+						*(uint8_t *)(dmibar+dmi_registers[i].addr),
+						dmi_registers[i].name);
+					break;
+			}
+		}
+	} else {
+		for (i = 0; i < size; i += 4) {
+			if (*(uint32_t *)(dmibar + i))
+				printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
+		}
 	}
 
 	unmap_physical((void *)dmibar, size);