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authorLee Leahy <leroy.p.leahy@intel.com>2016-01-29 14:35:13 -0800
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-02-02 19:00:35 +0100
commit95909924024687d42cdf34518d34d7c8eb1aee57 (patch)
tree7e536d1a0d45009527bcf7db53c873b4d4dfc4a5 /util/lint
parent05c0215ff31c80a06e3824fb55f5983b62f894cd (diff)
downloadcoreboot-95909924024687d42cdf34518d34d7c8eb1aee57.tar.xz
soc/intel/common: Use SoC specific routine to read/write MTRRs
The registers associated with the MTRRs for Quark are referenced through a port on the host bridge. Support the standard configurations by providing a weak routines which just do a rdmsr/wrmsr. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_MTRRS" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The MTRRs are displayed and * The message "FspTempRamExit returned successfully" is displayed TEST=Build and run on Galileo Change-Id: If2fea66d4b054be4555f5f172ea5945620648325 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13529 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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