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| author | Kane Chen <kane.chen@intel.com> | 2016-07-28 19:41:15 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-08-02 18:41:08 +0200 |
| commit | 597614347561f7a72ad3f9750f74d99a5cfe978e (patch) | |
| tree | 5cac6a37ef1ed0dd27377b4c4f0e859501d51626 /util/lint | |
| parent | d5817c887e2d0719fedaf89303bf72d04bf6be0f (diff) | |
| download | coreboot-597614347561f7a72ad3f9750f74d99a5cfe978e.tar.xz | |
google/reef: Add pull up 20K for LPC SERIRQ
per hw team's check and info from EDS, this pin needs to be pu 20K.
Otherwise SoC may not notice interrupt request from
EC over LPC because SERIRQ line is floating.
BUG=chrome-os-partner:55586
BRANCH=none
TEST=boot ok and Quanta factory verified the keyboard issue is gone
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a
Reviewed-on: https://review.coreboot.org/15951
Tested-by: build bot (Jenkins)
Reviewed-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'util/lint')
0 files changed, 0 insertions, 0 deletions