diff options
| author | Michael Büchler <michael.buechler@posteo.net> | 2020-09-09 01:04:27 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2020-09-12 10:50:33 +0000 |
| commit | 70fea013c7ebd6d85a7806748233fcfd76802f5f (patch) | |
| tree | 527de6bdb71fee30d2f985fe9ee4018d97cf75e7 /util/marvell/description.md | |
| parent | eea06570444de6b3e34de4b8be1c83e5ec75b3ac (diff) | |
| download | coreboot-70fea013c7ebd6d85a7806748233fcfd76802f5f.tar.xz | |
cpu/intel/model_1067x: enable PECI
This is required for Super I/Os to be able to read the CPU temperature
through PECI.
On 45nm Core 2 CPUs (Wolfdale, Yorkfield) it is not enabled by default.
This is probably related to erratum AW67 "Enabling PECI via the PECI_CTL
MSR incorrectly writes CPUID_FEATURE_MASK1 MSR". The suggested
workaround is "Do not initialize PECI before processor update is
loaded". Since coreboot performs microcode updates before running this
code it should not cause any trouble. It was tested on a Core 2 Duo
E8400, stepping E0.
PECI is already enabled by default on older (65nm) CPUs. Tested: Pentium
Dual-Core E2160.
See commit edac28ce65e48d6b2a0a2421d046a4fe4b2bf589 for the same change
on cpu/intel/model_6fx.
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I5a3ec033bd816665af4ecc82f7b167857cd7c1b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'util/marvell/description.md')
0 files changed, 0 insertions, 0 deletions