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authorMarc Jones <marc.jones@se-eng.com>2012-10-31 16:24:37 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-12 04:23:56 +0100
commit4adc8cdd185f46cd62f3bd17188761d3b0b1d87d (patch)
tree6bef9a659fea70f23a42d0c18d81ec3eef685150 /util/msrtool/configure
parent2a700ec16322561ad487e6ef1ae8878f9a7e4357 (diff)
downloadcoreboot-4adc8cdd185f46cd62f3bd17188761d3b0b1d87d.tar.xz
Add bd82x6x mainboards ASPM overrides.
The Intel PCH can override the ASPM settings via the MPC2 register. Add a chip override for F0-F7. Mainboards may implement this as needed. This also fixes the final PM setup being done too early. It was being done prior to the PCIe ASPM setup, which happens in the bridge scan. Change-Id: Idf2d2374899873fc6b1a2b00abdb683ea9f5bd6b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1796 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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