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| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-04-21 14:59:12 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-04-28 05:11:11 +0200 |
| commit | 1ba068550d70549580838ba675c8a6543c1d175d (patch) | |
| tree | ad3bffa2934d406efd853062aeb53be327f8938b /util/msrtool/intel_pentium4_later.c | |
| parent | d047ab590e525ae72aea117953250b25f71a1e60 (diff) | |
| download | coreboot-1ba068550d70549580838ba675c8a6543c1d175d.tar.xz | |
soc/intel/apollolake: Avoid marking 0xe0000-0xfffff region usable
coreboot writes RDSP at 0xf0000. Since depthcharge wipes usable
memory regions before starting, kernel can't find RDSP.
Change-Id: I584bd5d24248cf38f46342615cf3b0252a821b2a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'util/msrtool/intel_pentium4_later.c')
0 files changed, 0 insertions, 0 deletions