soc/intel/common/gpio_defs: Enable configuring GPIO_DW2 pad register

Currently all the helpers support configuring GPIO_DW0/1 registers. In
some architectures there is an additional configuration GPIO_DW2 register
that can be used to configure debounce duration etc. Add a helper macro
to enable configuring GPIO_DW2 pad register.

BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the current
configuration is not disturbed by turning on the GPIO_DEBUG option and
verifying the debug output before and after the change.

Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

0 files changed, 0 insertions, 0 deletions