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| author | Werner Zeh <werner.zeh@siemens.com> | 2018-11-22 15:10:18 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-23 11:28:52 +0000 |
| commit | 6b522c31aa55f1e09b63843e183c0f6f298a5605 (patch) | |
| tree | 6fdc7a84cbbc18ffdd8462aed58fd774c2eca8f5 /util/post | |
| parent | 697faf0d5fa1e4a8c221f083ab4b469d4a4b57d2 (diff) | |
| download | coreboot-6b522c31aa55f1e09b63843e183c0f6f298a5605.tar.xz | |
intelblocks/cpu: Fix wrong comment for P_Req field in PERF_CTL MSR
The mentioned bits 14:8 are wrong as the functions always write
bits 15:8. What happens is visible in the written code. There is no need
for an extra comment.
Change-Id: I59b4d24d01a0a8fa74912f9754e7bbb217ca269d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Diffstat (limited to 'util/post')
0 files changed, 0 insertions, 0 deletions