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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 17:47:06 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:31:36 +0000 |
| commit | 08143576466918413bfae2303abc4d0d16ae5b5c (patch) | |
| tree | e142830967562c879cc81b388b2c6e63d8d7366f /util/riscv | |
| parent | 93d9517795b58fca2639bc66e359a61219e82b81 (diff) | |
| download | coreboot-08143576466918413bfae2303abc4d0d16ae5b5c.tar.xz | |
nb/intel/ironlake: Add QPI Link register definitions
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: Id226a2fdcbd0fe48822c4f65746e14fb00db6b2e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions