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authorJonathan A. Kollasch <jakllsch@kollasch.net>2015-07-06 08:07:50 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2016-11-21 22:42:28 +0100
commit657d9cd5482835b49d79c7eabeb7baf2dce70dfe (patch)
tree7d9146d6fbf76c5ab50cdf74032bd9039516083f /util/riscvtools
parent7f1df8c0c13cf40d2eb74f7b13a3983ba7b3b3f2 (diff)
downloadcoreboot-657d9cd5482835b49d79c7eabeb7baf2dce70dfe.tar.xz
smscsuperio: map interrupt in smscsuperio_enable_serial()
This is a stopgap for when you use SUPERIO_SMSC_SMSCSUPERIO and the interrupt is unmapped at reset, but for whatever reason the chip is inaccessible in smscsuperio/superio.c::enable_dev() and thus the devicetree.cb IRQ information is not applied in ramstage and then serial console output fails to work for more than the UART FIFO depth in the OS. Change-Id: I00998088975569516f7caeb7f4098b48fe437889 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: https://review.coreboot.org/10807 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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