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| author | Aaron Durbin <adurbin@chromium.org> | 2016-10-27 09:53:17 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-10-28 19:01:48 +0200 |
| commit | 64606cea9394bf3b3a3803450f6e31c75800193c (patch) | |
| tree | 20ff0ad720f9d3098af636aca51b4d90942fd715 /util/rockchip | |
| parent | 11afdbf67c86097bbbf621bfafe76dedf6517379 (diff) | |
| download | coreboot-64606cea9394bf3b3a3803450f6e31c75800193c.tar.xz | |
soc/intel/skylake: don't hardcode GPE0 standard reg
While using '3' is fine for the standard gpe0 for skylake, I want
to make sure anyone that copies this code doesn't tweak GPE0_REG_MAX
without the hard coded index. If that does happen now things will
still work, but it may just not match the hardware proper.
BUG=chrome-os-partner:58666
Change-Id: I434b9a765a0a2f263490bb2b4ecb3635292d46c9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17160
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'util/rockchip')
0 files changed, 0 insertions, 0 deletions