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authorYinghai Lu <yinghailu@gmail.com>2005-07-08 02:49:49 +0000
committerYinghai Lu <yinghailu@gmail.com>2005-07-08 02:49:49 +0000
commit13f1c2af8be2cd7f7e99a678f5d428a65b771811 (patch)
tree27cad5581f1fa150f573149d48e82f70ba1b1d9f /util/romcc/Makefile
parent14cde9e96a777f9d75016a13b23fab0480515f58 (diff)
downloadcoreboot-13f1c2af8be2cd7f7e99a678f5d428a65b771811.tar.xz
eric patch
1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/romcc/Makefile')
-rw-r--r--util/romcc/Makefile6
1 files changed, 4 insertions, 2 deletions
diff --git a/util/romcc/Makefile b/util/romcc/Makefile
index c06777d7df..1734fe5c89 100644
--- a/util/romcc/Makefile
+++ b/util/romcc/Makefile
@@ -1,5 +1,3 @@
-
-
# Move the configuration defines to makefile.conf
CC=gcc
CPPFLAGS=
@@ -110,6 +108,10 @@ TESTS=\
simple_test84.c \
simple_test85.c \
simple_test86.c \
+ simple_test87.c \
+ simple_test88.c \
+ simple_test89.c \
+ simple_test90.c \
raminit_test1.c \
raminit_test2.c \
raminit_test3.c \