- O2, enums, and switch statements work in romcc

  - Support for compiling romcc on non x86 platforms
  - new romc options -msse and -mmmx for specifying extra registers to use
  - Bug fixes to device the device disable/enable framework and an amd8111 implementation
  - Move the link specification to the chip specification instead of the path
  - Allow specifying devices with internal bridges.
  - Initial via epia support
 - Opteron errata fixes


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

7 files changed, 149 insertions, 0 deletions

diff --git a/util/romcc/results/linux_test1.out b/util/romcc/results/linux_test1.out
new file mode 100644
index 0000000000..e139c33ef9
--- /dev/null
+++ b/util/romcc/results/linux_test1.out
diff --git a/util/romcc/results/linux_test2.out b/util/romcc/results/linux_test2.out
new file mode 100644
index 0000000000..ce61c099d2
--- /dev/null
+++ b/util/romcc/results/linux_test2.out
@@ -0,0 +1,59 @@
+setting up coherent ht domain....
+0000c040 <-00010101
+0000c044 <-00010101
+0000c048 <-00010101
+0000c04c <-00010101
+0000c050 <-00010101
+0000c054 <-00010101
+0000c058 <-00010101
+0000c05c <-00010101
+0000c068 <-0f00840f
+0000c06c <-00000070
+0000c084 <-11110020
+0000c088 <-00000200
+0000c094 <-00ff0000
+0000c144 <-003f0000
+0000c14c <-00000001
+0000c154 <-00000002
+0000c15c <-00000003
+0000c164 <-00000004
+0000c16c <-00000005
+0000c174 <-00000006
+0000c17c <-00000007
+0000c140 <-00000003
+0000c148 <-00400000
+0000c150 <-00400000
+0000c158 <-00400000
+0000c160 <-00400000
+0000c168 <-00400000
+0000c170 <-00400000
+0000c178 <-00400000
+0000c184 <-00e1ff00
+0000c18c <-00dfff00
+0000c194 <-00e3ff00
+0000c19c <-00000000
+0000c1a4 <-00000000
+0000c1ac <-00000000
+0000c1b4 <-00000b00
+0000c1bc <-00fe0b00
+0000c180 <-00e00003
+0000c188 <-00d80003
+0000c190 <-00e20003
+0000c198 <-00000000
+0000c1a0 <-00000000
+0000c1a8 <-00000000
+0000c1b0 <-00000a03
+0000c1b8 <-00400003
+0000c1c4 <-0000d000
+0000c1cc <-000ff000
+0000c1d4 <-00000000
+0000c1dc <-00000000
+0000c1c0 <-0000d003
+0000c1c8 <-00001013
+0000c1d0 <-00000000
+0000c1d8 <-00000000
+0000c1e0 <-ff000003
+0000c1e4 <-00000000
+0000c1e8 <-00000000
+0000c1ec <-00000000
+done.
diff --git a/util/romcc/results/linux_test3.out b/util/romcc/results/linux_test3.out
new file mode 100644
index 0000000000..06b38ce9d8
--- /dev/null
+++ b/util/romcc/results/linux_test3.out
@@ -0,0 +1,11 @@
+goto_test
+i = 00
+i = 01
+i = 02
+i = 03
+i = 04
+i = 05
+i = 06
+i = 07
+i = 08
+i = 09
diff --git a/util/romcc/results/linux_test4.out b/util/romcc/results/linux_test4.out
new file mode 100644
index 0000000000..5d69fe667c
--- /dev/null
+++ b/util/romcc/results/linux_test4.out
@@ -0,0 +1,11 @@
+cpu_socketA
+.up=0002 .down=ffff .across=0001
+.up=0003 .down=ffff .across=0000
+.up=ffff .down=0000 .across=0003
+.up=ffff .down=0001 .across=0002
+
+cpu_socketB
+.up=0002 .down=ffff .across=0001
+.up=0003 .down=ffff .across=0000
+.up=ffff .down=0000 .across=0003
+.up=ffff .down=0001 .across=0002
diff --git a/util/romcc/results/linux_test5.out b/util/romcc/results/linux_test5.out
new file mode 100644
index 0000000000..0c94914228
--- /dev/null
+++ b/util/romcc/results/linux_test5.out
@@ -0,0 +1,34 @@
+min_cycle_time: 75 min_latency: 02
+A
+B
+C
+C
+D
+E
+device: 00 new_cycle_time: 75 new_latency: 02
+G
+C
+D
+E
+G
+H
+device: 00 new_cycle_time: 75 new_latency: 02
+I
+device: 00 min_cycle_time: 75 min_latency: 02
+A
+B
+C
+C
+D
+E
+device: 01 new_cycle_time: 75 new_latency: 02
+G
+C
+D
+E
+G
+H
+device: 01 new_cycle_time: 75 new_latency: 02
+I
+device: 01 min_cycle_time: 75 min_latency: 02
+min_cycle_time: 75 min_latency: 02
diff --git a/util/romcc/results/linux_test6.out b/util/romcc/results/linux_test6.out
new file mode 100644
index 0000000000..5978e19e4a
--- /dev/null
+++ b/util/romcc/results/linux_test6.out
@@ -0,0 +1,2 @@
+B
+Registered
diff --git a/util/romcc/results/linux_test7.out b/util/romcc/results/linux_test7.out
new file mode 100644
index 0000000000..9d76d82734
--- /dev/null
+++ b/util/romcc/results/linux_test7.out
@@ -0,0 +1,32 @@
+val[00]: 0000c144 0000f8f8 00000000
+val[03]: 0000c14c 0000f8f8 00000001
+val[06]: 0000c154 0000f8f8 00000002
+val[09]: 0000c15c 0000f8f8 00000003
+val[0c]: 0000c164 0000f8f8 00000004
+val[0f]: 0000c16c 0000f8f8 00000005
+val[12]: 0000c174 0000f8f8 00000006
+val[15]: 0000c17c 0000f8f8 00000007
+val[00]: 0000c144 0000f8f8 00000000
+val[03]: 0000c14c 0000f8f8 00000001
+val[06]: 0000c154 0000f8f8 00000002
+val[09]: 0000c15c 0000f8f8 00000003
+val[0c]: 0000c164 0000f8f8 00000004
+val[0f]: 0000c16c 0000f8f8 00000005
+val[12]: 0000c174 0000f8f8 00000006
+val[15]: 0000c17c 0000f8f8 00000007
+val[00]: 0000c144 0000f8f8 00000000
+val[03]: 0000c14c 0000f8f8 00000001
+val[06]: 0000c154 0000f8f8 00000002
+val[09]: 0000c15c 0000f8f8 00000003
+val[0c]: 0000c164 0000f8f8 00000004
+val[0f]: 0000c16c 0000f8f8 00000005
+val[12]: 0000c174 0000f8f8 00000006
+val[15]: 0000c17c 0000f8f8 00000007
+val[00]: 0000c144 0000f8f8 00000000
+val[03]: 0000c14c 0000f8f8 00000001
+val[06]: 0000c154 0000f8f8 00000002
+val[09]: 0000c15c 0000f8f8 00000003
+val[0c]: 0000c164 0000f8f8 00000004
+val[0f]: 0000c16c 0000f8f8 00000005
+val[12]: 0000c174 0000f8f8 00000006
+val[15]: 0000c17c 0000f8f8 00000007