diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2009-06-30 15:17:49 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2009-06-30 15:17:49 +0000 |
commit | 0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch) | |
tree | 81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /util/romcc/tests/raminit_test.c | |
parent | 9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff) | |
download | coreboot-0867062412dd4bfe5a556e5f3fd85ba5b682d79b.tar.xz |
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/romcc/tests/raminit_test.c')
-rw-r--r-- | util/romcc/tests/raminit_test.c | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/util/romcc/tests/raminit_test.c b/util/romcc/tests/raminit_test.c index 9b6cf5d31c..2c6fa8c750 100644 --- a/util/romcc/tests/raminit_test.c +++ b/util/romcc/tests/raminit_test.c @@ -83,27 +83,27 @@ static void pcibios_write_config_dword( } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -125,7 +125,7 @@ static void pcibios_write_config_dword( int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -136,14 +136,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -151,14 +151,14 @@ void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } void __console_tx_char(unsigned char byte) |