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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-08-23 18:24:32 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-28 14:22:24 +0000 |
| commit | 8fda8f4ac3541441df97d96f4969037ddffd2de7 (patch) | |
| tree | ec3591ade6fc5b4cfd5a782da65aedd81318afef /util/romcc/tests/raminit_test.c | |
| parent | 3db0198358e1b8101d78a7c785e4f4efde4fcaf9 (diff) | |
| download | coreboot-8fda8f4ac3541441df97d96f4969037ddffd2de7.tar.xz | |
util/romcc: Fix typos
Change-Id: Ia9f0f1f527476900e6c54c60508600e16bea786f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'util/romcc/tests/raminit_test.c')
| -rw-r--r-- | util/romcc/tests/raminit_test.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/util/romcc/tests/raminit_test.c b/util/romcc/tests/raminit_test.c index b1baf7e49d..564786b51c 100644 --- a/util/romcc/tests/raminit_test.c +++ b/util/romcc/tests/raminit_test.c @@ -754,7 +754,7 @@ static void spd_set_dramc(void) { /* * Effects: Uses serial presence detect to set the - * DRAMC register, which records if ram is registerd or not, + * DRAMC register, which records if ram is registered or not, * and controls the refresh rate. * The refresh rate is not set here, as memory refresh * cannot be enbaled until after memory is initialized. @@ -997,7 +997,7 @@ static void spd_set_nbxcfg(void) } pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x53, reg); /* Now see if reg is 0xff. If it is we are done. If not, - * we need to set 0x18 into regster 0x50.l + * we need to set 0x18 into register 0x50.l * we will do this in two steps, first or in 0x80 to 0x50.b, * then or in 0x1 to 0x51.b */ |