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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-28 16:14:56 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-27 09:00:16 +0000 |
| commit | 945b698f82279fdb42f83f6a3eb2e6f74db2869c (patch) | |
| tree | 3eac3bd7ec5032441081d89a370acddf8f3e5f5b /util/romcc/tests/simple_test3.c | |
| parent | c2092569d5d21e0cdd3690d8021c2d46dfeaeabd (diff) | |
| download | coreboot-945b698f82279fdb42f83f6a3eb2e6f74db2869c.tar.xz | |
util/romcc: Drop romcc support
Finally all boards use a GCC compiled bootblock!
Change-Id: I0c9a1b19dbdc32b43875da7d685718bae9d7f5f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37337
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/romcc/tests/simple_test3.c')
| -rw-r--r-- | util/romcc/tests/simple_test3.c | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/util/romcc/tests/simple_test3.c b/util/romcc/tests/simple_test3.c deleted file mode 100644 index 864760c418..0000000000 --- a/util/romcc/tests/simple_test3.c +++ /dev/null @@ -1,38 +0,0 @@ -static void spd_set_drb(void) -{ - /* - * Effects: Uses serial presence detect to set the - * DRB registers which holds the ending memory address assigned - * to each DIMM. - */ - unsigned end_of_memory; - unsigned device; - - end_of_memory = 0; /* in multiples of 8MiB */ - device = 0x50; - while (device <= 0x53) { - unsigned side1_bits, side2_bits; - int byte, byte2; - - side1_bits = side2_bits = -1; - - /* rows */ - byte = -1; - if (1) { - /* now I have the ram size in bits as a power of two (less 1) */ - /* Make it mulitples of 8MB */ - side1_bits -= 25; - } - - /* Compute the end address for the DRB register */ - /* Only process dimms < 2GB (2^8 * 8MB) */ - if (1) { - end_of_memory += side1_bits; - } - __builtin_outl(end_of_memory, 0x1234); - - if (1) { - end_of_memory += side2_bits; - } - } -} |