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author | Eric Biederman <ebiederm@xmission.com> | 2003-06-28 06:49:45 +0000 |
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committer | Eric Biederman <ebiederm@xmission.com> | 2003-06-28 06:49:45 +0000 |
commit | d1ea53995ca8c385db79174d9b2fa133fd52b0aa (patch) | |
tree | a2c40289914c50d0f7409ddf90c9a6c3b2485447 /util/romcc/tests/simple_test45.c | |
parent | db59928fd93080e5376e45f7dcf7ddee0262e336 (diff) | |
download | coreboot-d1ea53995ca8c385db79174d9b2fa133fd52b0aa.tar.xz |
- Update romcc so that it more successfully spills registers to the xmm registers
- Add several more test cases.
- Bump the version number to .32
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/romcc/tests/simple_test45.c')
-rw-r--r-- | util/romcc/tests/simple_test45.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/util/romcc/tests/simple_test45.c b/util/romcc/tests/simple_test45.c new file mode 100644 index 0000000000..beb041708c --- /dev/null +++ b/util/romcc/tests/simple_test45.c @@ -0,0 +1,41 @@ +static void spd_set_memclk(void) +{ + unsigned min_cycle_time; + unsigned device; + int new_cycle_time, new_latency; + int index; + int latency; + + min_cycle_time = 0x50; + device = 0x50; + new_cycle_time = 0xa0; + new_latency = 5; + + + latency = 0; + for(index = 0; index < 3; index++, latency++) { + unsigned long loops; + loops = 1000000; + do { + unsigned short val; + val = __builtin_inw(0x10e0); + } while(--loops); + if (!loops) { + continue; + } + + __builtin_outb(device, 0xe4); + __builtin_outb(index, 0xe8); + + loops = 1000000; + while(--loops) + ; + } + if (new_latency > 4){ + return; + } + + if (new_cycle_time > min_cycle_time) { + min_cycle_time = new_cycle_time; + } +} |