diff options
| author | Eric Biederman <ebiederm@xmission.com> | 2003-10-11 06:20:25 +0000 |
|---|---|---|
| committer | Eric Biederman <ebiederm@xmission.com> | 2003-10-11 06:20:25 +0000 |
| commit | 83b991afff40e12a8b6756af06a472842edb1a66 (patch) | |
| tree | a441ff0d88afcb0a07cf22dc3653db3e07a05c98 /util/romcc/tests/simple_test67.c | |
| parent | 080038bfbd8fdf08bac12476a3789495e6f705ca (diff) | |
| download | coreboot-83b991afff40e12a8b6756af06a472842edb1a66.tar.xz | |
- O2, enums, and switch statements work in romcc
- Support for compiling romcc on non x86 platforms
- new romc options -msse and -mmmx for specifying extra registers to use
- Bug fixes to device the device disable/enable framework and an amd8111 implementation
- Move the link specification to the chip specification instead of the path
- Allow specifying devices with internal bridges.
- Initial via epia support
- Opteron errata fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/romcc/tests/simple_test67.c')
| -rw-r--r-- | util/romcc/tests/simple_test67.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/util/romcc/tests/simple_test67.c b/util/romcc/tests/simple_test67.c new file mode 100644 index 0000000000..3bfdc5a072 --- /dev/null +++ b/util/romcc/tests/simple_test67.c @@ -0,0 +1,24 @@ +static void main(void) +{ + unsigned int dch, dcl; +/* HERE I AM async_lat */ + unsigned async_lat; + int dimms; + dimms = 1; + async_lat = 0; + dch = 0x1234; + dcl = __builtin_inl(0x5678); + if (!(dcl & (1 << 8))) { + if (dimms == 4) { + async_lat = 9; + } + else { + async_lat = 8; + } + } + else { + async_lat = 6; + } + dch |= async_lat; + __builtin_outl(dch, 0x9abc); +} |