- Update romcc to version 0.27 and add more tests.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

16 files changed, 3096 insertions, 10 deletions

diff --git a/util/romcc/tests/hello_world2.c b/util/romcc/tests/hello_world2.c
new file mode 100644
index 0000000000..7990dcb518
--- /dev/null
+++ b/util/romcc/tests/hello_world2.c
@@ -0,0 +1,127 @@
+void outb(unsigned char value, unsigned short port)
+{
+	__builtin_outb(value, port);
+}
+
+unsigned char inb(unsigned short port)
+{
+	return __builtin_inb(port);
+}
+
+/* Base Address */
+#ifndef TTYS0_BASE
+#define TTYS0_BASE 0x3f8
+#endif
+
+#ifndef TTYS0_BAUD
+#define TTYS0_BAUD 115200
+#endif
+
+#if ((115200%TTYS0_BAUD) != 0)
+#error Bad ttys0 baud rate
+#endif
+
+#if TTYS0_BAUD == 115200
+#define TTYS0_DIV (1)
+#else
+#define TTYS0_DIV	(115200/TTYS0_BAUD)
+#endif
+
+/* Line Control Settings */
+#ifndef TTYS0_LCS
+/* Set 8bit, 1 stop bit, no parity */
+#define TTYS0_LCS	0x3
+#endif
+
+#define UART_LCS	TTYS0_LCS
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+int uart_can_tx_byte(void)
+{
+	return inb(TTYS0_BASE + UART_LSR) & 0x20;
+}
+
+void uart_wait_to_tx_byte(void)
+{
+	while(!uart_can_tx_byte())
+		;
+}
+
+void uart_wait_until_sent(void)
+{
+	while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) 
+		;
+}
+
+static void uart_tx_byte(unsigned char data)
+{
+	uart_wait_to_tx_byte();
+	outb(data, TTYS0_BASE + UART_TBR);
+	/* Make certain the data clears the fifos */
+	uart_wait_until_sent();
+}
+
+
+void uart_init(void)
+{
+	/* disable interrupts */
+	outb(0x0, TTYS0_BASE + UART_IER);
+	/* enable fifo's */
+	outb(0x01, TTYS0_BASE + UART_FCR);
+	/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
+	outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
+	outb(TTYS0_DIV & 0xFF,   TTYS0_BASE + UART_DLL);
+	outb((TTYS0_DIV >> 8) & 0xFF,    TTYS0_BASE + UART_DLM);
+	outb(UART_LCS, TTYS0_BASE + UART_LCR);
+}
+
+
+void __console_tx_char(unsigned char byte)
+{
+	uart_tx_byte(byte);
+		
+}
+
+void __console_tx_string(char *str)
+{
+	unsigned char ch;
+	while((ch = *str++) != '\0') {
+		__console_tx_char(ch);
+	}
+}
+
+
+void print_debug_char(unsigned char byte) { __console_tx_char(byte); }
+void print_debug(char *str) { __console_tx_string(str); }
+
+void main(void)
+{
+	static const char msg[] = "hello world\r\n";
+	uart_init();
+#if 0
+	print_debug(msg);
+#endif
+#if 1
+	print_debug("hello world\r\n");
+#endif
+	while(1) {
+		;
+	}
+}
diff --git a/util/romcc/tests/ldscript.ld b/util/romcc/tests/ldscript.ld
new file mode 100644
index 0000000000..97b307fc66
--- /dev/null
+++ b/util/romcc/tests/ldscript.ld
@@ -0,0 +1,20 @@
+
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0x1000;
+	.text . : {
+		. = ALIGN(16);
+		_start = . ;
+		*(.rom.text);
+		*(.text)
+		. = ALIGN(16);
+	}
+	.data . : {
+		. = ALIGN(16);
+		*(.rom.data);
+		*(.data)
+		. = ALIGN(16);
+	}
+}
\ No newline at end of file
diff --git a/util/romcc/tests/raminit_test.c b/util/romcc/tests/raminit_test.c
index 8dd9c977e5..9b6cf5d31c 100644
--- a/util/romcc/tests/raminit_test.c
+++ b/util/romcc/tests/raminit_test.c
@@ -1,7 +1,8 @@
 #define HAVE_STRING_SUPPORT          0
-#define HAVE_CAST_SUPPORT            0
-#define HAVE_STATIC_ARRAY_SUPPORT    0
-#define HAVE_POINTER_SUPPORT         0
+#define HAVE_CAST_SUPPORT            1
+#define HAVE_STATIC_ARRAY_SUPPORT    1
+#define HAVE_POINTER_SUPPORT         1
+#define HAVE_MACRO_ARG_SUPPORT       0
 
 void outb(unsigned char value, unsigned short port)
 {
@@ -196,7 +197,7 @@ void __console_tx_string(char *str)
 {
 	unsigned char ch;
 	while((ch = *str++) != '\0') {
-		__console_tx_byte(ch);
+		__console_tx_char(ch);
 	}
 }
 #else
@@ -1112,7 +1113,11 @@ static void dimms_read(unsigned long offset)
 		print_debug("\n");
 #endif
 #if HAVE_POINTER_SUPPORT
+#if HAVE_MACRO_ARG_SUPPORT
 		dummy = RAM(unsigned long, addr);
+#else
+		dummy = *((volatile unsigned long *)(addr));
+#endif
 #endif
 #if HAVE_STRING_SUPPORT
 		print_debug("Reading "); 
@@ -1120,7 +1125,11 @@ static void dimms_read(unsigned long offset)
 		print_debug("\n");
 #endif
 #if HAVE_POINTER_SUPPORT
+#if HAVE_MACRO_ARG_SUPPORT
 		dummy = RAM(unsigned long, addr ^ 0xdff8);
+#else
+		dummy = *((volatile unsigned long *)(addr ^ 0xdff8));
+#endif
 #endif
 #if HAVE_STRING_SUPPORT
 		print_debug("Read "); 
diff --git a/util/romcc/tests/raminit_test2.c b/util/romcc/tests/raminit_test2.c
index 8dd9c977e5..68747a7a91 100644
--- a/util/romcc/tests/raminit_test2.c
+++ b/util/romcc/tests/raminit_test2.c
@@ -1,7 +1,8 @@
-#define HAVE_STRING_SUPPORT          0
-#define HAVE_CAST_SUPPORT            0
-#define HAVE_STATIC_ARRAY_SUPPORT    0
-#define HAVE_POINTER_SUPPORT         0
+#define HAVE_STRING_SUPPORT          1
+#define HAVE_CAST_SUPPORT            1
+#define HAVE_STATIC_ARRAY_SUPPORT    1
+#define HAVE_POINTER_SUPPORT         1
+#define HAVE_MACRO_ARG_SUPPORT       0
 
 void outb(unsigned char value, unsigned short port)
 {
@@ -196,7 +197,7 @@ void __console_tx_string(char *str)
 {
 	unsigned char ch;
 	while((ch = *str++) != '\0') {
-		__console_tx_byte(ch);
+		__console_tx_char(ch);
 	}
 }
 #else
@@ -1112,7 +1113,11 @@ static void dimms_read(unsigned long offset)
 		print_debug("\n");
 #endif
 #if HAVE_POINTER_SUPPORT
+#if HAVE_MACRO_ARG_SUPPORT
 		dummy = RAM(unsigned long, addr);
+#else
+		dummy = *((volatile unsigned long *)(addr));
+#endif
 #endif
 #if HAVE_STRING_SUPPORT
 		print_debug("Reading "); 
@@ -1120,7 +1125,11 @@ static void dimms_read(unsigned long offset)
 		print_debug("\n");
 #endif
 #if HAVE_POINTER_SUPPORT
+#if HAVE_MACRO_ARG_SUPPORT
 		dummy = RAM(unsigned long, addr ^ 0xdff8);
+#else
+		dummy = *((volatile unsigned long *)(addr ^ 0xdff8));
+#endif
 #endif
 #if HAVE_STRING_SUPPORT
 		print_debug("Read "); 
diff --git a/util/romcc/tests/raminit_test3.c b/util/romcc/tests/raminit_test3.c
new file mode 100644
index 0000000000..dc3b4760c2
--- /dev/null
+++ b/util/romcc/tests/raminit_test3.c
@@ -0,0 +1,1076 @@
+# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+# 1 "<built-in>"
+# 1 "<command line>"
+# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+
+# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/arch/i386/include/stdint.h" 1
+# 11 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/arch/i386/include/stdint.h"
+typedef unsigned char uint8_t;
+typedef signed char int8_t;
+
+typedef unsigned short uint16_t;
+typedef signed short int16_t;
+
+typedef unsigned int uint32_t;
+typedef signed int int32_t;
+
+
+
+
+
+
+
+typedef unsigned char uint_least8_t;
+typedef signed char int_least8_t;
+
+typedef unsigned short uint_least16_t;
+typedef signed short int_least16_t;
+
+typedef unsigned int uint_least32_t;
+typedef signed int int_least32_t;
+
+
+
+
+
+
+
+typedef unsigned char uint_fast8_t;
+typedef signed char int_fast8_t;
+
+typedef unsigned int uint_fast16_t;
+typedef signed int int_fast16_t;
+
+typedef unsigned int uint_fast32_t;
+typedef signed int int_fast32_t;
+
+
+
+
+
+
+
+typedef int intptr_t;
+typedef unsigned int uintptr_t;
+
+
+
+
+
+
+typedef long int intmax_t;
+typedef unsigned long int uintmax_t;
+# 3 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2
+# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/include/device/pci_def.h" 1
+# 4 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2
+# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/arch/i386/include/arch/romcc_io.h" 1
+static void outb(unsigned char value, unsigned short port)
+{
+        __builtin_outb(value, port);
+}
+
+static void outw(unsigned short value, unsigned short port)
+{
+        __builtin_outw(value, port);
+}
+
+static void outl(unsigned int value, unsigned short port)
+{
+        __builtin_outl(value, port);
+}
+
+
+static unsigned char inb(unsigned short port)
+{
+        return __builtin_inb(port);
+}
+
+
+static unsigned char inw(unsigned short port)
+{
+        return __builtin_inw(port);
+}
+
+static unsigned char inl(unsigned short port)
+{
+        return __builtin_inl(port);
+}
+
+static void hlt(void)
+{
+        __builtin_hlt();
+}
+
+typedef __builtin_msr_t msr_t;
+
+static msr_t rdmsr(unsigned long index)
+{
+        return __builtin_rdmsr(index);
+}
+
+static void wrmsr(unsigned long index, msr_t msr)
+{
+        __builtin_wrmsr(index, msr.lo, msr.hi);
+}
+
+
+
+
+
+
+
+static unsigned char pci_read_config8(unsigned addr)
+{
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        return inb(0xCFC + (addr & 3));
+}
+
+static unsigned short pci_read_config16(unsigned addr)
+{
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        return inw(0xCFC + (addr & 2));
+}
+
+static unsigned int pci_read_config32(unsigned addr)
+{
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        return inl(0xCFC);
+}
+
+static void pci_write_config8(unsigned addr, unsigned char value)
+{
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outb(value, 0xCFC + (addr & 3));
+}
+
+static void pci_write_config16(unsigned addr, unsigned short value)
+{
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outw(value, 0xCFC + (addr & 2));
+}
+
+static void pci_write_config32(unsigned addr, unsigned int value)
+{
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outl(value, 0xCFC);
+}
+# 5 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2
+# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/pc80/serial.c" 1
+# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/include/part/fallback_boot.h" 1
+# 2 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/pc80/serial.c" 2
+# 44 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/pc80/serial.c"
+static int uart_can_tx_byte(void)
+{
+        return inb(0x3f8 + 0x05) & 0x20;
+}
+
+static void uart_wait_to_tx_byte(void)
+{
+        while(!uart_can_tx_byte())
+                ;
+}
+
+static void uart_wait_until_sent(void)
+{
+        while(!(inb(0x3f8 + 0x05) & 0x40))
+                ;
+}
+
+static void uart_tx_byte(unsigned char data)
+{
+        uart_wait_to_tx_byte();
+        outb(data, 0x3f8 + 0x00);
+
+        uart_wait_until_sent();
+}
+
+static void uart_init(void)
+{
+
+        outb(0x0, 0x3f8 + 0x01);
+
+        outb(0x01, 0x3f8 + 0x02);
+
+        outb(0x80 | 0x3, 0x3f8 + 0x03);
+# 89 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/pc80/serial.c"
+                outb((115200/9600) & 0xFF, 0x3f8 + 0x00);
+                outb(((115200/9600) >> 8) & 0xFF, 0x3f8 + 0x01);
+
+        outb(0x3, 0x3f8 + 0x03);
+}
+# 6 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2
+# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/arch/i386/lib/console.c" 1
+# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/include/console/loglevel.h" 1
+# 2 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/arch/i386/lib/console.c" 2
+
+static void __console_tx_byte(unsigned char byte)
+{
+        uart_tx_byte(byte);
+}
+
+static void __console_tx_nibble(unsigned nibble)
+{
+        unsigned char digit;
+        digit = nibble + '0';
+        if (digit > '9') {
+                digit += 39;
+        }
+        __console_tx_byte(digit);
+}
+
+static void __console_tx_char(int loglevel, unsigned char byte)
+{
+        if (8 > loglevel) {
+                uart_tx_byte(byte);
+        }
+}
+
+static void __console_tx_hex8(int loglevel, unsigned char value)
+{
+        if (8 > loglevel) {
+                __console_tx_nibble((value >> 4U) & 0x0fU);
+                __console_tx_nibble(value & 0x0fU);
+        }
+}
+
+static void __console_tx_hex16(int loglevel, unsigned short value)
+{
+        if (8 > loglevel) {
+                __console_tx_nibble((value >> 12U) & 0x0fU);
+                __console_tx_nibble((value >> 8U) & 0x0fU);
+                __console_tx_nibble((value >> 4U) & 0x0fU);
+                __console_tx_nibble(value & 0x0fU);
+        }
+}
+
+static void __console_tx_hex32(int loglevel, unsigned int value)
+{
+        if (8 > loglevel) {
+                __console_tx_nibble((value >> 28U) & 0x0fU);
+                __console_tx_nibble((value >> 24U) & 0x0fU);
+                __console_tx_nibble((value >> 20U) & 0x0fU);
+                __console_tx_nibble((value >> 16U) & 0x0fU);
+                __console_tx_nibble((value >> 12U) & 0x0fU);
+                __console_tx_nibble((value >> 8U) & 0x0fU);
+                __console_tx_nibble((value >> 4U) & 0x0fU);
+                __console_tx_nibble(value & 0x0fU);
+        }
+}
+
+static void __console_tx_string(int loglevel, const char *str)
+{
+        if (8 > loglevel) {
+                unsigned char ch;
+                while((ch = *str++) != '\0') {
+                        __console_tx_byte(ch);
+                }
+        }
+}
+
+static void print_emerg_char(unsigned char byte) { __console_tx_char(0, byte); }
+static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(0, value); }
+static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(0, value); }
+static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(0, value); }
+static void print_emerg(const char *str) { __console_tx_string(0, str); }
+
+static void print_alert_char(unsigned char byte) { __console_tx_char(1, byte); }
+static void print_alert_hex8(unsigned char value) { __console_tx_hex8(1, value); }
+static void print_alert_hex16(unsigned short value){ __console_tx_hex16(1, value); }
+static void print_alert_hex32(unsigned int value) { __console_tx_hex32(1, value); }
+static void print_alert(const char *str) { __console_tx_string(1, str); }
+
+static void print_crit_char(unsigned char byte) { __console_tx_char(2, byte); }
+static void print_crit_hex8(unsigned char value) { __console_tx_hex8(2, value); }
+static void print_crit_hex16(unsigned short value){ __console_tx_hex16(2, value); }
+static void print_crit_hex32(unsigned int value) { __console_tx_hex32(2, value); }
+static void print_crit(const char *str) { __console_tx_string(2, str); }
+
+static void print_err_char(unsigned char byte) { __console_tx_char(3, byte); }
+static void print_err_hex8(unsigned char value) { __console_tx_hex8(3, value); }
+static void print_err_hex16(unsigned short value){ __console_tx_hex16(3, value); }
+static void print_err_hex32(unsigned int value) { __console_tx_hex32(3, value); }
+static void print_err(const char *str) { __console_tx_string(3, str); }
+
+static void print_warning_char(unsigned char byte) { __console_tx_char(4, byte); }
+static void print_warning_hex8(unsigned char value) { __console_tx_hex8(4, value); }
+static void print_warning_hex16(unsigned short value){ __console_tx_hex16(4, value); }
+static void print_warning_hex32(unsigned int value) { __console_tx_hex32(4, value); }
+static void print_warning(const char *str) { __console_tx_string(4, str); }
+
+static void print_notice_char(unsigned char byte) { __console_tx_char(5, byte); }
+static void print_notice_hex8(unsigned char value) { __console_tx_hex8(5, value); }
+static void print_notice_hex16(unsigned short value){ __console_tx_hex16(5, value); }
+static void print_notice_hex32(unsigned int value) { __console_tx_hex32(5, value); }
+static void print_notice(const char *str) { __console_tx_string(5, str); }
+
+static void print_info_char(unsigned char byte) { __console_tx_char(6, byte); }
+static void print_info_hex8(unsigned char value) { __console_tx_hex8(6, value); }
+static void print_info_hex16(unsigned short value){ __console_tx_hex16(6, value); }
+static void print_info_hex32(unsigned int value) { __console_tx_hex32(6, value); }
+static void print_info(const char *str) { __console_tx_string(6, str); }
+
+static void print_debug_char(unsigned char byte) { __console_tx_char(7, byte); }
+static void print_debug_hex8(unsigned char value) { __console_tx_hex8(7, value); }
+static void print_debug_hex16(unsigned short value){ __console_tx_hex16(7, value); }
+static void print_debug_hex32(unsigned int value) { __console_tx_hex32(7, value); }
+static void print_debug(const char *str) { __console_tx_string(7, str); }
+
+static void print_spew_char(unsigned char byte) { __console_tx_char(8, byte); }
+static void print_spew_hex8(unsigned char value) { __console_tx_hex8(8, value); }
+static void print_spew_hex16(unsigned short value){ __console_tx_hex16(8, value); }
+static void print_spew_hex32(unsigned int value) { __console_tx_hex32(8, value); }
+static void print_spew(const char *str) { __console_tx_string(8, str); }
+# 128 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/arch/i386/lib/console.c"
+static void console_init(void)
+{
+        static const char console_test[] =
+                "\r\n\r\nLinuxBIOS-"
+                "1.1.0"
+                ".0Fallback"
+                " "
+                "Mon Jun 9 18:15:20 MDT 2003"
+                " starting...\r\n";
+        print_info(console_test);
+}
+# 7 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2
+# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/ram/ramtest.c" 1
+static void write_phys(unsigned long addr, unsigned long value)
+{
+        volatile unsigned long *ptr;
+        ptr = (void *)addr;
+        *ptr = value;
+}
+
+static unsigned long read_phys(unsigned long addr)
+{
+        volatile unsigned long *ptr;
+        ptr = (void *)addr;
+        return *ptr;
+}
+
+void ram_fill(unsigned long start, unsigned long stop)
+{
+        unsigned long addr;
+
+
+
+        print_debug("DRAM fill: ");
+        print_debug_hex32(start);
+        print_debug("-");
+        print_debug_hex32(stop);
+        print_debug("\r\n");
+        for(addr = start; addr < stop ; addr += 4) {
+
+                if ((addr & 0xffff) == 0) {
+                        print_debug_hex32(addr);
+                        print_debug("\r");
+                }
+                write_phys(addr, addr);
+        };
+
+        print_debug_hex32(addr);
+        print_debug("\r\nDRAM filled\r\n");
+}
+
+void ram_verify(unsigned long start, unsigned long stop)
+{
+        unsigned long addr;
+
+
+
+        print_debug("DRAM verify: ");
+        print_debug_hex32(start);
+        print_debug_char('-');
+        print_debug_hex32(stop);
+        print_debug("\r\n");
+        for(addr = start; addr < stop ; addr += 4) {
+                unsigned long value;
+
+                if ((addr & 0xffff) == 0) {
+                        print_debug_hex32(addr);
+                        print_debug("\r");
+                }
+                value = read_phys(addr);
+                if (value != addr) {
+
+                        print_err_hex32(addr);
+                        print_err_char(':');
+                        print_err_hex32(value);
+                        print_err("\r\n");
+                }
+        }
+
+        print_debug_hex32(addr);
+        print_debug("\r\nDRAM verified\r\n");
+}
+
+
+void ramcheck(unsigned long start, unsigned long stop)
+{
+        int result;
+
+
+
+
+
+        print_debug("Testing DRAM : ");
+        print_debug_hex32(start);
+        print_debug("-");
+        print_debug_hex32(stop);
+        print_debug("\r\n");
+        ram_fill(start, stop);
+        ram_verify(start, stop);
+        print_debug("Done.\n");
+}
+# 8 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2
+
+static void die(const char *str)
+{
+        print_emerg(str);
+        do {
+                hlt();
+        } while(1);
+}
+
+
+
+
+static void sdram_set_registers(void)
+{
+        static const unsigned int register_values[] = {
+# 51 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x003f0000,
+
+
+
+
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007,
+# 93 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000003,
+
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00400000,
+# 145 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00e1ff00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00dfff00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00e3ff00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000b00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00fe0b00,
+# 180 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00e00003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00d80003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00e20003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000a03,
+
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00400003,
+# 219 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x0000d000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x000ff000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000,
+# 249 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x0000d003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00001013,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000,
+# 290 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000,
+# 316 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x40) & 0xFF)), 0x001f01fe, 0x00000001,
+
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x44) & 0xFF)), 0x001f01fe, 0x01000001,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x48) & 0xFF)), 0x001f01fe, 0x02000001,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x001f01fe, 0x03000001,
+
+
+
+
+
+
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x50) & 0xFF)), 0x001f01fe, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x54) & 0xFF)), 0x001f01fe, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x58) & 0xFF)), 0x001f01fe, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x001f01fe, 0x00000000,
+# 351 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x60) & 0xFF)), 0xC01f01ff, 0x00e0fe00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x64) & 0xFF)), 0xC01f01ff, 0x00e0fe00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x68) & 0xFF)), 0xC01f01ff, 0x00e0fe00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xC01f01ff, 0x00e0fe00,
+
+
+
+
+
+
+
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x70) & 0xFF)), 0xC01f01ff, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x74) & 0xFF)), 0xC01f01ff, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x78) & 0xFF)), 0xC01f01ff, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x7C) & 0xFF)), 0xC01f01ff, 0x00000000,
+# 387 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x80) & 0xFF)), 0xffff8888, 0x00000033,
+# 456 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x88) & 0xFF)), 0xe8088008, 0x03623125,
+# 487 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x8c) & 0xFF)), 0xff8fe08e, 0x00000930,
+# 563 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)), 0xf0000000,
+        (4 << 25)|(0 << 24)|
+        (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)|
+        (1 << 19)|(1 << 18)|(0 << 17)|(0 << 16)|
+        (2 << 14)|(0 << 13)|(0 << 12)|
+        (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)|
+        (0 << 3) |(0 << 1) |(0 << 0),
+# 635 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x94) & 0xFF)), 0xc180f0f0, 0x0e2b0a05,
+# 655 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x98) & 0xFF)), 0xfc00ffff, 0x00000000,
+# 689 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) | ((0x58) & 0xFF)), 0xffe0e0e0, 0x00000000,
+# 698 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000003e, 0x00000000,
+
+
+
+
+
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) | ((0x60) & 0xFF)), 0xffffff00, 0x00000000,
+        };
+        int i;
+        int max;
+        print_debug("setting up CPU0 northbridge registers\r\n");
+        max = sizeof(register_values)/sizeof(register_values[0]);
+        for(i = 0; i < max; i += 3) {
+                unsigned long reg;
+
+
+
+
+
+
+                reg = pci_read_config32(register_values[i]);
+                reg &= register_values[i+1];
+                reg |= register_values[i+2];
+                pci_write_config32(register_values[i], reg);
+        }
+        print_debug("done.\r\n");
+}
+# 743 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+static void sdram_set_spd_registers(void)
+{
+        unsigned long dcl;
+        dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)));
+
+        dcl &= ~(1<<17);
+        pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)), dcl);
+}
+
+
+static void sdram_enable(void)
+{
+        unsigned long dcl;
+
+
+        dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)));
+        print_debug("dcl: ");
+        print_debug_hex32(dcl);
+        print_debug("\r\n");
+        dcl |= (1<<3);
+        pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)), dcl);
+        dcl &= ~(1<<3);
+        dcl &= ~(1<<0);
+        dcl &= ~(1<<1);
+        dcl &= ~(1<<2);
+        dcl |= (1<<8);
+        pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)), dcl);
+
+        print_debug("Initializing memory: ");
+        int loops = 0;
+        do {
+                dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)));
+                loops += 1;
+                if ((loops & 1023) == 0) {
+                        print_debug(".");
+                }
+        } while(((dcl & (1<<8)) != 0) && (loops < 300000));
+        if (loops >= 300000) {
+                print_debug(" failed\r\n");
+        } else {
+                print_debug(" done\r\n");
+        }
+# 803 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+}
+
+static void sdram_first_normal_reference(void) {}
+static void sdram_enable_refresh(void) {}
+static void sdram_special_finishup(void) {}
+
+# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/sdram/generic_sdram.c" 1
+void sdram_no_memory(void)
+{
+        print_err("No memory!!\r\n");
+        while(1) {
+                hlt();
+        }
+}
+
+
+void sdram_initialize(void)
+{
+        print_debug("Ram1\r\n");
+
+        sdram_set_registers();
+
+        print_debug("Ram2\r\n");
+
+        sdram_set_spd_registers();
+
+        print_debug("Ram3\r\n");
+
+
+
+
+        sdram_enable();
+
+        print_debug("Ram4\r\n");
+        sdram_first_normal_reference();
+
+        print_debug("Ram5\r\n");
+        sdram_enable_refresh();
+        sdram_special_finishup();
+
+        print_debug("Ram6\r\n");
+}
+# 810 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2
+
+static int boot_cpu(void)
+{
+        volatile unsigned long *local_apic;
+        unsigned long apic_id;
+        int bsp;
+        msr_t msr;
+        msr = rdmsr(0x1b);
+        bsp = !!(msr.lo & (1 << 8));
+        if (bsp) {
+                print_debug("Bootstrap cpu\r\n");
+        }
+
+        return bsp;
+}
+
+static int cpu_init_detected(void)
+{
+        unsigned long dcl;
+        int cpu_init;
+
+        unsigned long htic;
+
+        htic = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x6c) & 0xFF)));
+# 849 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        cpu_init = (htic & (1<<6));
+        if (cpu_init) {
+                print_debug("CPU INIT Detected.\r\n");
+        }
+        return cpu_init;
+}
+
+static void setup_coherent_ht_domain(void)
+{
+        static const unsigned int register_values[] = {
+# 884 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x44) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x48) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x4c) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x50) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x54) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x58) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x5c) & 0xFF)), 0xfff0f0f0, 0x00010101,
+# 983 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x68) & 0xFF)), 0x00800000, 0x0f00840f,
+# 1005 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4),
+# 1082 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00009c05, 0x11110020,
+# 1127 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x88) & 0xFF)), 0xfffff0ff, 0x00000200,
+# 1148 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x94) & 0xFF)), 0xff000000, 0x00ff0000,
+# 1182 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x003f0000,
+
+
+
+
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007,
+# 1224 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000003,
+
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00400000,
+# 1276 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00e1ff00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00dfff00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00e3ff00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000b00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00fe0b00,
+# 1311 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00e00003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00d80003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00e20003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000a03,
+
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00400003,
+# 1350 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x0000d000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x000ff000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000,
+# 1380 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x0000d003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00001013,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000,
+# 1421 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000,
+
+        };
+        int i;
+        int max;
+        print_debug("setting up coherent ht domain....\r\n");
+        max = sizeof(register_values)/sizeof(register_values[0]);
+        for(i = 0; i < max; i += 3) {
+                unsigned long reg;
+
+
+
+
+
+
+                reg = pci_read_config32(register_values[i]);
+                reg &= register_values[i+1];
+                reg |= register_values[i+2] & ~register_values[i+1];
+                pci_write_config32(register_values[i], reg);
+        }
+        print_debug("done.\r\n");
+}
+
+static void enumerate_ht_chain(void)
+{
+        unsigned next_unitid, last_unitid;;
+        next_unitid = 1;
+        do {
+                uint32_t id;
+                uint8_t hdr_type, pos;
+                last_unitid = next_unitid;
+
+                id = pci_read_config32(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x00) & 0xFF)));
+
+                if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+                        (((id >> 16) & 0xffff) == 0xffff) ||
+                        (((id >> 16) & 0xffff) == 0x0000)) {
+                        break;
+                }
+                hdr_type = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x0e) & 0xFF)));
+                pos = 0;
+                hdr_type &= 0x7f;
+
+                if ((hdr_type == 0) ||
+                        (hdr_type == 1)) {
+                        pos = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x34) & 0xFF)));
+                }
+                while(pos != 0) {
+                        uint8_t cap;
+                        cap = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((pos + 0) & 0xFF)));
+                        if (cap == 0x08) {
+                                uint16_t flags;
+                                flags = pci_read_config16(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((pos + 2) & 0xFF)));
+                                if ((flags >> 13) == 0) {
+                                        unsigned count;
+                                        flags &= ~0x1f;
+                                        flags |= next_unitid & 0x1f;
+                                        count = (flags >> 5) & 0x1f;
+                                        pci_write_config16(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((pos + 2) & 0xFF)), flags);
+                                        next_unitid += count;
+                                        break;
+                                }
+                        }
+                        pos = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((pos + 1) & 0xFF)));
+                }
+        } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
+}
+
+static void print_pci_devices(void)
+{
+        uint32_t addr;
+        for(addr = ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0) & 0xFF));
+                addr <= ( (((0) & 0xFF) << 16) | (((0x1f) & 0x1f) << 11) | (((0x7) & 0x07) << 8) | ((0) & 0xFF));
+                addr += ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0) & 0xFF))) {
+                uint32_t id;
+                id = pci_read_config32(addr + 0x00);
+                if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+                        (((id >> 16) & 0xffff) == 0xffff) ||
+                        (((id >> 16) & 0xffff) == 0x0000)) {
+                        continue;
+                }
+                print_debug("PCI: 00:");
+                print_debug_hex8(addr >> 11);
+                print_debug_char('.');
+                print_debug_hex8((addr >> 8) & 7);
+                print_debug("\r\n");
+        }
+}
+# 1525 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+static void enable_smbus(void)
+{
+        uint32_t addr;
+        for(addr = ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0) & 0xFF));
+                addr <= ( (((0) & 0xFF) << 16) | (((0x1f) & 0x1f) << 11) | (((0x7) & 0x07) << 8) | ((0) & 0xFF));
+                addr += ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0) & 0xFF))) {
+                uint32_t id;
+                id = pci_read_config32(addr);
+                if (id == ((0x746b << 16) | (0x1022))) {
+                        break;
+                }
+        }
+        if (addr > ( (((0) & 0xFF) << 16) | (((0x1f) & 0x1f) << 11) | (((0x7) & 0x07) << 8) | ((0) & 0xFF))) {
+                die("SMBUS controller not found\r\n");
+        }
+        uint8_t enable;
+        print_debug("SMBus controller enabled\r\n");
+        pci_write_config32(addr + 0x58, 0x1000 | 1);
+        enable = pci_read_config8(addr + 0x41);
+        pci_write_config8(addr + 0x41, enable | (1 << 7));
+}
+
+
+static inline void smbus_delay(void)
+{
+        outb(0x80, 0x80);
+}
+
+static int smbus_wait_until_ready(void)
+{
+        unsigned long loops;
+        loops = (100*1000*10);
+        do {
+                unsigned short val;
+                smbus_delay();
+                val = inw(0x1000 + 0xe0);
+                if ((val & 0x800) == 0) {
+                        break;
+                }
+        } while(--loops);
+        return loops?0:-1;
+}
+
+static int smbus_wait_until_done(void)
+{
+        unsigned long loops;
+        loops = (100*1000*10);
+        do {
+                unsigned short val;
+                smbus_delay();
+
+                val = inw(0x1000 + 0xe0);
+                if (((val & 0x8) == 0) || ((val & 0x437) != 0)) {
+                        break;
+                }
+        } while(--loops);
+        return loops?0:-1;
+}
+
+static int smbus_read_byte(unsigned device, unsigned address)
+{
+        unsigned char global_control_register;
+        unsigned char global_status_register;
+        unsigned char byte;
+
+        if (smbus_wait_until_ready() < 0) {
+                return -1;
+        }
+
+
+
+        outw(inw(0x1000 + 0xe2) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), 0x1000 + 0xe2);
+
+        outw(((device & 0x7f) << 1) | 1, 0x1000 + 0xe4);
+
+        outb(address & 0xFF, 0x1000 + 0xe8);
+
+        outw((inw(0x1000 + 0xe2) & ~7) | (0x2), 0x1000 + 0xe2);
+
+
+
+        outw(inw(0x1000 + 0xe0), 0x1000 + 0xe0);
+
+
+        outw(0, 0x1000 + 0xe6);
+
+
+        outw((inw(0x1000 + 0xe2) | (1 << 3)), 0x1000 + 0xe2);
+
+
+
+        if (smbus_wait_until_done() < 0) {
+                return -1;
+        }
+
+        global_status_register = inw(0x1000 + 0xe0);
+
+
+        byte = inw(0x1000 + 0xe6) & 0xff;
+
+        if (global_status_register != (1 << 4)) {
+                return -1;
+        }
+        return byte;
+}
+
+static void dump_spd_registers(void)
+{
+        unsigned device;
+        device = (0xa << 3);
+        print_debug("\r\n");
+        while(device <= ((0xa << 3) +1)) {
+                int i;
+                print_debug("dimm: ");
+                print_debug_hex8(device);
+                for(i = 0; i < 256; i++) {
+                        int status;
+                        unsigned char byte;
+                        if ((i & 0xf) == 0) {
+                                print_debug("\r\n");
+                                print_debug_hex8(i);
+                                print_debug(": ");
+                        }
+                        status = smbus_read_byte(device, i);
+                        if (status < 0) {
+                                print_debug("bad device\r\n");
+                                continue;
+                        }
+                        byte = status & 0xff;
+                        print_debug_hex8(byte);
+                        print_debug_char(' ');
+                }
+                device += 1;
+                print_debug("\r\n");
+        }
+}
+
+static void dump_spd_registers1(void)
+{
+        int i;
+        print_debug("dimm: ");
+        print_debug_hex8((0xa << 3));
+        for(i = 0; i < 256; i++) {
+                int status;
+                unsigned char byte;
+                if ((i & 0xf) == 0) {
+                        print_debug("\r\n");
+                        print_debug_hex8(i);
+                        print_debug(": ");
+                }
+                status = smbus_read_byte((0xa << 3), i);
+                if (status < 0) {
+                        print_debug("bad device\r\n");
+                        break;
+                }
+                byte = status & 0xff;
+                print_debug_hex8(byte);
+                print_debug_char(' ');
+        }
+        print_debug("\r\n");
+}
+
+
+
+static void dump_spd_registers2(void)
+{
+        unsigned dev;
+        print_debug("\r\n");
+        for(dev = (0xa << 3); dev <= ((0xa << 3) +1); dev += 1) {
+                print_debug("dimm: ");
+                print_debug_hex8(dev);
+                int status;
+                unsigned char byte;
+                status = smbus_read_byte(dev, 0);
+                if (status < 0) {
+                        print_debug("bad device\r\n");
+                        continue;
+                }
+                byte = status & 0xff;
+                print_debug_hex8(byte);
+                print_debug("\r\n");
+        }
+}
+
+static void main(void)
+{
+        uart_init();
+        console_init();
+        if (boot_cpu() && !cpu_init_detected()) {
+                setup_coherent_ht_domain();
+                enumerate_ht_chain();
+                print_pci_devices();
+                enable_smbus();
+                sdram_initialize();
+
+
+
+                dump_spd_registers1();
+                dump_spd_registers2();
+
+
+
+
+
+                ram_fill( 0x00000000, 0x00001000);
+                ram_verify(0x00000000, 0x00001000);
+
+
+
+
+
+        }
+}
diff --git a/util/romcc/tests/simple_test21.c b/util/romcc/tests/simple_test21.c
new file mode 100644
index 0000000000..7f7b87122b
--- /dev/null
+++ b/util/romcc/tests/simple_test21.c
@@ -0,0 +1,6 @@
+
+
+static void main(void)
+{
+	asm("hlt");
+}
diff --git a/util/romcc/tests/simple_test22.c b/util/romcc/tests/simple_test22.c
new file mode 100644
index 0000000000..247369b80b
--- /dev/null
+++ b/util/romcc/tests/simple_test22.c
@@ -0,0 +1,306 @@
+struct syscall_result {
+	long val;
+	int errno;
+};
+
+static struct syscall_result syscall_return(long result)
+{
+	struct syscall_result res;
+	if (((unsigned long)result) >= ((unsigned long)-125)) {
+		res.errno = - result;
+		res.val = -1;
+	} else {
+		res.errno = 0;
+		res.val = result;
+	}
+	return res;
+}
+
+static struct syscall_result syscall0(unsigned long nr)
+{
+	long res;
+	asm volatile(
+		"int $0x80"
+		: "a" (res)
+		: "a" (nr));
+	return syscall_return(res);
+}
+
+static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
+{
+	long res;
+	asm volatile(
+		"int $0x80"
+		: "a" (res)
+		: "a" (nr), "b" (arg1));
+	return syscall_return(res);
+	
+}
+
+static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
+{
+	long res;
+	asm volatile(
+		"int $0x80"
+		: "a" (res)
+		: "a" (nr), "b" (arg1), "c" (arg2));
+	return syscall_return(res);
+	
+}
+
+
+static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2,
+	unsigned long arg3)
+{
+	long res;
+	asm volatile(
+		"int $0x80"
+		: "a" (res)
+		: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
+	return syscall_return(res);
+	
+}
+
+static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
+	unsigned long arg3, unsigned long arg4)
+{
+	long res;
+	asm volatile(
+		"int $0x80"
+		: "a" (res)
+		: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
+	return syscall_return(res);
+	
+}
+
+static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
+	unsigned long arg3, unsigned long arg4, unsigned long arg5)
+{
+	long res;
+	asm volatile(
+		"int $0x80"
+		: "a" (res)
+		: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), 
+		"S" (arg4), "D" (arg5));
+	return syscall_return(res);
+	
+}
+
+#define NR_exit                 1
+#define NR_fork                 2
+#define NR_read                 3
+#define NR_write                4
+#define NR_open                 5
+#define NR_close                6
+#define NR_waitpid              7
+#define NR_creat                8
+#define NR_link                 9
+#define NR_unlink              10
+#define NR_execve              11
+#define NR_chdir               12
+#define NR_time                13
+#define NR_mknod               14
+#define NR_chmod               15
+#define NR_lchown              16
+#define NR_break               17
+#define NR_oldstat             18
+#define NR_lseek               19
+#define NR_getpid              20
+#define NR_mount               21
+#define NR_umount              22
+#define NR_setuid              23
+#define NR_getuid              24
+#define NR_stime               25
+#define NR_ptrace              26
+#define NR_alarm               27
+#define NR_oldfstat            28
+#define NR_pause               29
+#define NR_utime               30
+#define NR_stty                31
+#define NR_gtty                32
+#define NR_access              33
+#define NR_nice                34
+#define NR_ftime               35
+#define NR_sync                36
+#define NR_kill                37
+#define NR_rename              38
+#define NR_mkdir               39
+#define NR_rmdir               40
+#define NR_dup                 41
+#define NR_pipe                42
+#define NR_times               43
+#define NR_prof                44
+#define NR_brk                 45
+#define NR_setgid              46
+#define NR_getgid              47
+#define NR_signal              48
+#define NR_geteuid             49
+#define NR_getegid             50
+#define NR_acct                51
+#define NR_umount2             52
+#define NR_lock                53
+#define NR_ioctl               54
+#define NR_fcntl               55
+#define NR_mpx                 56
+#define NR_setpgid             57
+#define NR_ulimit              58
+#define NR_oldolduname         59
+#define NR_umask               60
+#define NR_chroot              61
+#define NR_ustat               62
+#define NR_dup2                63
+#define NR_getppid             64
+#define NR_getpgrp             65
+#define NR_setsid              66
+#define NR_sigaction           67
+#define NR_sgetmask            68
+#define NR_ssetmask            69
+#define NR_setreuid            70
+#define NR_setregid            71
+#define NR_sigsuspend          72
+#define NR_sigpending          73
+#define NR_sethostname         74
+#define NR_setrlimit           75
+#define NR_getrlimit           76
+#define NR_getrusage           77
+#define NR_gettimeofday        78
+#define NR_settimeofday        79
+#define NR_getgroups           80
+#define NR_setgroups           81
+#define NR_select              82
+#define NR_symlink             83
+#define NR_oldlstat            84
+#define NR_readlink            85
+#define NR_uselib              86
+#define NR_swapon              87
+#define NR_reboot              88
+#define NR_readdir             89
+#define NR_mmap                90
+#define NR_munmap              91
+#define NR_truncate            92
+#define NR_ftruncate           93
+#define NR_fchmod              94
+#define NR_fchown              95
+#define NR_getpriority         96
+#define NR_setpriority         97
+#define NR_profil              98
+#define NR_statfs              99
+#define NR_fstatfs            100
+#define NR_ioperm             101
+#define NR_socketcall         102
+#define NR_syslog             103
+#define NR_setitimer          104
+#define NR_getitimer          105
+#define NR_stat               106
+#define NR_lstat              107
+#define NR_fstat              108
+#define NR_olduname           109
+#define NR_iopl               110
+#define NR_vhangup            111
+#define NR_idle               112
+#define NR_vm86old            113
+#define NR_wait4              114
+#define NR_swapoff            115
+#define NR_sysinfo            116
+#define NR_ipc                117
+#define NR_fsync              118
+#define NR_sigreturn          119
+#define NR_clone              120
+#define NR_setdomainname      121
+#define NR_uname              122
+#define NR_modify_ldt         123
+#define NR_adjtimex           124
+#define NR_mprotect           125
+#define NR_sigprocmask        126
+#define NR_create_module      127
+#define NR_init_module        128
+#define NR_delete_module      129
+#define NR_get_kernel_syms    130
+#define NR_quotactl           131
+#define NR_getpgid            132
+#define NR_fchdir             133
+#define NR_bdflush            134
+#define NR_sysfs              135
+#define NR_personality        136
+#define NR_afs_syscall        137 /* Syscall for Andrew File System */
+#define NR_setfsuid           138
+#define NR_setfsgid           139
+#define NR__llseek            140
+#define NR_getdents           141
+#define NR__newselect         142
+#define NR_flock              143
+#define NR_msync              144
+#define NR_readv              145
+#define NR_writev             146
+#define NR_getsid             147
+#define NR_fdatasync          148
+#define NR__sysctl            149
+#define NR_mlock              150
+#define NR_munlock            151
+#define NR_mlockall           152
+#define NR_munlockall         153
+#define NR_sched_setparam             154
+#define NR_sched_getparam             155
+#define NR_sched_setscheduler         156
+#define NR_sched_getscheduler         157
+#define NR_sched_yield                158
+#define NR_sched_get_priority_max     159
+#define NR_sched_get_priority_min     160
+#define NR_sched_rr_get_interval      161
+#define NR_nanosleep          162
+#define NR_mremap             163
+#define NR_setresuid          164
+#define NR_getresuid          165
+#define NR_vm86               166
+#define NR_query_module       167
+#define NR_poll               168
+#define NR_nfsservctl         169
+#define NR_setresgid          170
+#define NR_getresgid          171
+#define NR_prctl              172
+#define NR_rt_sigreturn       173
+#define NR_rt_sigaction       174
+#define NR_rt_sigprocmask     175
+#define NR_rt_sigpending      176
+#define NR_rt_sigtimedwait    177
+#define NR_rt_sigqueueinfo    178
+#define NR_rt_sigsuspend      179
+#define NR_pread              180
+#define NR_pwrite             181
+#define NR_chown              182
+#define NR_getcwd             183
+#define NR_capget             184
+#define NR_capset             185
+#define NR_sigaltstack        186
+#define NR_sendfile           187
+#define NR_getpmsg            188     /* some people actually want streams */
+#define NR_putpmsg            189     /* some people actually want streams */
+#define NR_vfork              190
+
+typedef long ssize_t;
+typedef unsigned long size_t;
+
+/* Standard file descriptors */
+#define STDIN_FILENO    0  /* Standard input */
+#define STDOUT_FILENO   1  /* Standard output */
+#define STDERR_FILENO   2  /* Standard error output */
+
+static ssize_t write(int fd, const void *buf, size_t count)
+{
+	struct syscall_result res;
+	res = syscall3(NR_write, fd, (unsigned long)buf, count);
+	return res.val;
+}
+
+static void _exit(int status)
+{
+	struct syscall_result res;
+	res = syscall1(NR_exit, status);
+}
+
+static void main(void)
+{
+	static const char msg[] = "hello world\r\n";
+	write(STDOUT_FILENO, msg, sizeof(msg));
+	_exit(0);
+}
diff --git a/util/romcc/tests/simple_test23.c b/util/romcc/tests/simple_test23.c
new file mode 100644
index 0000000000..33acd047a2
--- /dev/null
+++ b/util/romcc/tests/simple_test23.c
@@ -0,0 +1,18 @@
+static void print(char *str)
+{
+	while(1) {
+		unsigned char ch;
+		ch = *str;
+		if (ch == '\0') {
+			break;
+		}
+		__builtin_outb(ch, 0x1234);
+		str += 1;
+	}
+}
+
+static void main(void)
+{
+	print("hello world\r\n");
+	print("how are you today\r\n");
+}
diff --git a/util/romcc/tests/simple_test24.c b/util/romcc/tests/simple_test24.c
new file mode 100644
index 0000000000..01413c2dad
--- /dev/null
+++ b/util/romcc/tests/simple_test24.c
@@ -0,0 +1,16 @@
+void smbus_read_byte(void)
+{
+	unsigned char host_status_register;
+	unsigned char byte;
+	int result;
+
+	host_status_register = __builtin_inb(0x1234);
+
+	/* read results of transaction */
+	byte = __builtin_inb(0x4567);
+
+	result = byte;
+	if (host_status_register != 0x02) {
+		result = -1;
+	}
+}
diff --git a/util/romcc/tests/simple_test25.c b/util/romcc/tests/simple_test25.c
new file mode 100644
index 0000000000..80ddfa6740
--- /dev/null
+++ b/util/romcc/tests/simple_test25.c
@@ -0,0 +1,109 @@
+#define COUNT 26
+static void main(void)
+{
+	unsigned char a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r, s, t, u, v, w, x, y, z;
+	a = 1;
+	b = 2;
+	c = 3;
+	d = 4;
+	e = 5;
+	f = 6;
+	g = 7;
+	h = 8;
+	i = 9;
+	j = 10;
+	k = 11;
+	l = 12;
+	m = 13;
+	n = 14;
+	o = 15;
+	p = 16;
+	q = 17;
+	r = 18;
+	s = 19;
+	t = 20;
+	u = 21;
+	v = 22;
+	w = 23;
+	x = 24;
+	y = 25;
+	z = 26;
+#if COUNT >= 26
+	__builtin_outb(z, 0xab);
+#endif
+#if COUNT >= 25
+	__builtin_outb(y, 0xab);
+#endif
+#if COUNT >= 24
+	__builtin_outb(x, 0xab);
+#endif
+#if COUNT >= 23
+	__builtin_outb(w, 0xab);
+#endif
+#if COUNT >= 22
+	__builtin_outb(v, 0xab);
+#endif
+#if COUNT >= 21
+	__builtin_outb(u, 0xab);
+#endif
+#if COUNT >= 20
+	__builtin_outb(t, 0xab);
+#endif
+#if COUNT >= 19
+	__builtin_outb(s, 0xab);
+#endif
+#if COUNT >= 18
+	__builtin_outb(r, 0xab);
+#endif
+#if COUNT >= 17
+	__builtin_outb(q, 0xab);
+#endif
+#if COUNT >= 16
+	__builtin_outb(p, 0xab);
+#endif
+#if COUNT >= 15
+	__builtin_outb(o, 0xab);
+#endif
+#if COUNT >= 14
+	__builtin_outb(n, 0xab);
+#endif
+#if COUNT >= 13
+	__builtin_outb(m, 0xab);
+#endif
+#if COUNT >= 12
+	__builtin_outb(l, 0xab);
+#endif
+#if COUNT >= 11
+	__builtin_outb(k, 0xab);
+#endif
+#if COUNT >= 10
+	__builtin_outb(j, 0xab);
+#endif
+#if COUNT >= 9
+	__builtin_outb(i, 0xab);
+#endif
+#if COUNT >= 8
+	__builtin_outb(h, 0xab);
+#endif
+#if COUNT >= 7
+	__builtin_outb(g, 0xab);
+#endif
+#if COUNT >= 6
+	__builtin_outb(f, 0xab);
+#endif
+#if COUNT >= 5
+	__builtin_outb(e, 0xab);
+#endif
+#if COUNT >= 4
+	__builtin_outb(d, 0xab);
+#endif
+#if COUNT >= 3
+	__builtin_outb(c, 0xab);
+#endif
+#if COUNT >= 2
+	__builtin_outb(b, 0xab);
+#endif
+#if COUNT >= 1
+	__builtin_outb(a, 0xab);
+#endif
+}
diff --git a/util/romcc/tests/simple_test26.c b/util/romcc/tests/simple_test26.c
new file mode 100644
index 0000000000..b26bbb2ed7
--- /dev/null
+++ b/util/romcc/tests/simple_test26.c
@@ -0,0 +1,109 @@
+#define COUNT 23
+static void main(void)
+{
+	unsigned int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r, s, t, u, v, w, x, y, z;
+	a = __builtin_inb(0xab);
+	b = __builtin_inb(0xab);
+	c = __builtin_inb(0xab);
+	d = __builtin_inb(0xab);
+	e = __builtin_inb(0xab);
+	f = __builtin_inb(0xab);
+	g = __builtin_inb(0xab);
+	h = __builtin_inb(0xab);
+	i = __builtin_inb(0xab);
+	j = __builtin_inb(0xab);
+	k = __builtin_inb(0xab);
+	l = __builtin_inb(0xab);
+	m = __builtin_inb(0xab);
+	n = __builtin_inb(0xab);
+	o = __builtin_inb(0xab);
+	p = __builtin_inb(0xab);
+	q = __builtin_inb(0xab);
+	r = __builtin_inb(0xab);
+	s = __builtin_inb(0xab);
+	t = __builtin_inb(0xab);
+	u = __builtin_inb(0xab);
+	v = __builtin_inb(0xab);
+	w = __builtin_inb(0xab);
+	x = __builtin_inb(0xab);
+	y = __builtin_inb(0xab);
+	z = __builtin_inb(0xab);
+#if COUNT >= 26
+	__builtin_outb(z, 0xab);
+#endif
+#if COUNT >= 25
+	__builtin_outb(y, 0xab);
+#endif
+#if COUNT >= 24
+	__builtin_outb(x, 0xab);
+#endif
+#if COUNT >= 23
+	__builtin_outb(w, 0xab);
+#endif
+#if COUNT >= 22
+	__builtin_outb(v, 0xab);
+#endif
+#if COUNT >= 21
+	__builtin_outb(u, 0xab);
+#endif
+#if COUNT >= 20
+	__builtin_outb(t, 0xab);
+#endif
+#if COUNT >= 19
+	__builtin_outb(s, 0xab);
+#endif
+#if COUNT >= 18
+	__builtin_outb(r, 0xab);
+#endif
+#if COUNT >= 17
+	__builtin_outb(q, 0xab);
+#endif
+#if COUNT >= 16
+	__builtin_outb(p, 0xab);
+#endif
+#if COUNT >= 15
+	__builtin_outb(o, 0xab);
+#endif
+#if COUNT >= 14
+	__builtin_outb(n, 0xab);
+#endif
+#if COUNT >= 13
+	__builtin_outb(m, 0xab);
+#endif
+#if COUNT >= 12
+	__builtin_outb(l, 0xab);
+#endif
+#if COUNT >= 11
+	__builtin_outb(k, 0xab);
+#endif
+#if COUNT >= 10
+	__builtin_outb(j, 0xab);
+#endif
+#if COUNT >= 9
+	__builtin_outb(i, 0xab);
+#endif
+#if COUNT >= 8
+	__builtin_outb(h, 0xab);
+#endif
+#if COUNT >= 7
+	__builtin_outb(g, 0xab);
+#endif
+#if COUNT >= 6
+	__builtin_outb(f, 0xab);
+#endif
+#if COUNT >= 5
+	__builtin_outb(e, 0xab);
+#endif
+#if COUNT >= 4
+	__builtin_outb(d, 0xab);
+#endif
+#if COUNT >= 3
+	__builtin_outb(c, 0xab);
+#endif
+#if COUNT >= 2
+	__builtin_outb(b, 0xab);
+#endif
+#if COUNT >= 1
+	__builtin_outb(a, 0xab);
+#endif
+}
diff --git a/util/romcc/tests/simple_test27.c b/util/romcc/tests/simple_test27.c
new file mode 100644
index 0000000000..d40e43f1c4
--- /dev/null
+++ b/util/romcc/tests/simple_test27.c
@@ -0,0 +1,133 @@
+void outb(unsigned char value, unsigned short port)
+{
+	__builtin_outb(value, port);
+}
+
+unsigned char inb(unsigned short port)
+{
+	return __builtin_inb(port);
+}
+
+/* Base Address */
+#ifndef TTYS0_BASE
+#define TTYS0_BASE 0x3f8
+#endif
+
+#ifndef TTYS0_BAUD
+#define TTYS0_BAUD 115200
+#endif
+
+#if ((115200%TTYS0_BAUD) != 0)
+#error Bad ttys0 baud rate
+#endif
+
+#if TTYS0_BAUD == 115200
+#define TTYS0_DIV (1)
+#else
+#define TTYS0_DIV	(115200/TTYS0_BAUD)
+#endif
+
+/* Line Control Settings */
+#ifndef TTYS0_LCS
+/* Set 8bit, 1 stop bit, no parity */
+#define TTYS0_LCS	0x3
+#endif
+
+#define UART_LCS	TTYS0_LCS
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+int uart_can_tx_byte(void)
+{
+	return inb(TTYS0_BASE + UART_LSR) & 0x20;
+}
+
+void uart_wait_to_tx_byte(void)
+{
+	while(!uart_can_tx_byte())
+		;
+}
+
+void uart_wait_until_sent(void)
+{
+	while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) 
+		;
+}
+
+static void uart_tx_byte(unsigned char data)
+{
+	uart_wait_to_tx_byte();
+	outb(data, TTYS0_BASE + UART_TBR);
+	/* Make certain the data clears the fifos */
+	uart_wait_until_sent();
+}
+
+
+void uart_init(void)
+{
+	/* disable interrupts */
+	outb(0x0, TTYS0_BASE + UART_IER);
+	/* enable fifo's */
+	outb(0x01, TTYS0_BASE + UART_FCR);
+	/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
+	outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
+	outb(TTYS0_DIV & 0xFF,   TTYS0_BASE + UART_DLL);
+	outb((TTYS0_DIV >> 8) & 0xFF,    TTYS0_BASE + UART_DLM);
+	outb(UART_LCS, TTYS0_BASE + UART_LCR);
+}
+
+
+void __console_tx_char(unsigned char byte)
+{
+	uart_tx_byte(byte);
+		
+}
+
+void __console_tx_string(char *str)
+{
+	unsigned char ch;
+	while((ch = *str++) != '\0') {
+		__console_tx_char(ch);
+	}
+}
+
+
+void print_debug_char(unsigned char byte) { __console_tx_char(byte); }
+void print_debug(char *str) { __console_tx_string(str); }
+
+void main(void)
+{
+	static const char msg[] = "hello world\r\n";
+	uart_init();
+#if 0
+	print_debug(msg);
+#endif
+#if 1
+	print_debug("hello world\r\n");
+	print_debug("how are you today\r\n");
+#endif
+	while(1) {
+		;
+	}
+}
+
+void main2(void)
+{
+	main();
+}
diff --git a/util/romcc/tests/simple_test28.c b/util/romcc/tests/simple_test28.c
new file mode 100644
index 0000000000..8d83383124
--- /dev/null
+++ b/util/romcc/tests/simple_test28.c
@@ -0,0 +1,24 @@
+static void outl(unsigned int value, unsigned short port)
+{
+        __builtin_outl(value, port);
+}
+
+static unsigned char inl(unsigned short port)
+{
+        return __builtin_inl(port);
+}
+
+
+static void setup_coherent_ht_domain(void)
+{
+        static const unsigned int register_values[] = {
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101,
+
+        };
+	unsigned long reg;
+	reg = inl(0xFC);
+	reg &= register_values[1];
+	reg |= register_values[2] & ~register_values[1];
+	outl(register_values[0], 0xF8);
+	outl(reg, 0xFC);
+}
diff --git a/util/romcc/tests/simple_test29.c b/util/romcc/tests/simple_test29.c
new file mode 100644
index 0000000000..7eb8f4fa75
--- /dev/null
+++ b/util/romcc/tests/simple_test29.c
@@ -0,0 +1,37 @@
+static void outb(unsigned char value, unsigned short port)
+{
+        __builtin_outb(value, port);
+}
+
+static unsigned char inb(unsigned short port)
+{
+        return __builtin_inb(port);
+}
+
+static void __console_tx_byte(unsigned char byte)
+{
+	while(inb(0x3f8 + 0x05))
+		;
+	outb(byte, 0x3f8 + 0x00);
+}
+
+static void __console_tx_string(int loglevel, const char *str)
+{
+        if (8 > loglevel) {
+                unsigned char ch;
+                while((ch = *str++) != '\0') {
+                        __console_tx_byte(ch);
+                }
+        }
+}
+static void console_init(void)
+{
+        static const char console_test[] =
+                "\r\n\r\nLinuxBIOS-"
+                "1.1.0"
+                ".0Fallback"
+                " "
+                "Mon Jun 9 18:15:20 MDT 2003"
+                " starting...\r\n";
+        __console_tx_string(6, console_test);
+}
diff --git a/util/romcc/tests/simple_test30.c b/util/romcc/tests/simple_test30.c
new file mode 100644
index 0000000000..fc21fc6833
--- /dev/null
+++ b/util/romcc/tests/simple_test30.c
@@ -0,0 +1,1087 @@
+struct syscall_result {
+	long val;
+	int errno;
+};
+
+static struct syscall_result syscall_return(long result)
+{
+	struct syscall_result res;
+	if (((unsigned long)result) >= ((unsigned long)-125)) {
+		res.errno = - result;
+		res.val = -1;
+	} else {
+		res.errno = 0;
+		res.val = result;
+	}
+	return res;
+}
+
+static struct syscall_result syscall0(unsigned long nr)
+{
+	long res;
+	asm volatile(
+		"int $0x80"
+		: "a" (res)
+		: "a" (nr));
+	return syscall_return(res);
+}
+
+static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
+{
+	long res;
+	asm volatile(
+		"int $0x80"
+		: "a" (res)
+		: "a" (nr), "b" (arg1));
+	return syscall_return(res);
+	
+}
+
+static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
+{
+	long res;
+	asm volatile(
+		"int $0x80"
+		: "a" (res)
+		: "a" (nr), "b" (arg1), "c" (arg2));
+	return syscall_return(res);
+	
+}
+
+
+static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2,
+	unsigned long arg3)
+{
+	long res;
+	asm volatile(
+		"int $0x80"
+		: "a" (res)
+		: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
+	return syscall_return(res);
+	
+}
+
+static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
+	unsigned long arg3, unsigned long arg4)
+{
+	long res;
+	asm volatile(
+		"int $0x80"
+		: "a" (res)
+		: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
+	return syscall_return(res);
+	
+}
+
+static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
+	unsigned long arg3, unsigned long arg4, unsigned long arg5)
+{
+	long res;
+	asm volatile(
+		"int $0x80"
+		: "a" (res)
+		: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), 
+		"S" (arg4), "D" (arg5));
+	return syscall_return(res);
+	
+}
+
+#define NR_exit                 1
+#define NR_fork                 2
+#define NR_read                 3
+#define NR_write                4
+#define NR_open                 5
+#define NR_close                6
+#define NR_waitpid              7
+#define NR_creat                8
+#define NR_link                 9
+#define NR_unlink              10
+#define NR_execve              11
+#define NR_chdir               12
+#define NR_time                13
+#define NR_mknod               14
+#define NR_chmod               15
+#define NR_lchown              16
+#define NR_break               17
+#define NR_oldstat             18
+#define NR_lseek               19
+#define NR_getpid              20
+#define NR_mount               21
+#define NR_umount              22
+#define NR_setuid              23
+#define NR_getuid              24
+#define NR_stime               25
+#define NR_ptrace              26
+#define NR_alarm               27
+#define NR_oldfstat            28
+#define NR_pause               29
+#define NR_utime               30
+#define NR_stty                31
+#define NR_gtty                32
+#define NR_access              33
+#define NR_nice                34
+#define NR_ftime               35
+#define NR_sync                36
+#define NR_kill                37
+#define NR_rename              38
+#define NR_mkdir               39
+#define NR_rmdir               40
+#define NR_dup                 41
+#define NR_pipe                42
+#define NR_times               43
+#define NR_prof                44
+#define NR_brk                 45
+#define NR_setgid              46
+#define NR_getgid              47
+#define NR_signal              48
+#define NR_geteuid             49
+#define NR_getegid             50
+#define NR_acct                51
+#define NR_umount2             52
+#define NR_lock                53
+#define NR_ioctl               54
+#define NR_fcntl               55
+#define NR_mpx                 56
+#define NR_setpgid             57
+#define NR_ulimit              58
+#define NR_oldolduname         59
+#define NR_umask               60
+#define NR_chroot              61
+#define NR_ustat               62
+#define NR_dup2                63
+#define NR_getppid             64
+#define NR_getpgrp             65
+#define NR_setsid              66
+#define NR_sigaction           67
+#define NR_sgetmask            68
+#define NR_ssetmask            69
+#define NR_setreuid            70
+#define NR_setregid            71
+#define NR_sigsuspend          72
+#define NR_sigpending          73
+#define NR_sethostname         74
+#define NR_setrlimit           75
+#define NR_getrlimit           76
+#define NR_getrusage           77
+#define NR_gettimeofday        78
+#define NR_settimeofday        79
+#define NR_getgroups           80
+#define NR_setgroups           81
+#define NR_select              82
+#define NR_symlink             83
+#define NR_oldlstat            84
+#define NR_readlink            85
+#define NR_uselib              86
+#define NR_swapon              87
+#define NR_reboot              88
+#define NR_readdir             89
+#define NR_mmap                90
+#define NR_munmap              91
+#define NR_truncate            92
+#define NR_ftruncate           93
+#define NR_fchmod              94
+#define NR_fchown              95
+#define NR_getpriority         96
+#define NR_setpriority         97
+#define NR_profil              98
+#define NR_statfs              99
+#define NR_fstatfs            100
+#define NR_ioperm             101
+#define NR_socketcall         102
+#define NR_syslog             103
+#define NR_setitimer          104
+#define NR_getitimer          105
+#define NR_stat               106
+#define NR_lstat              107
+#define NR_fstat              108
+#define NR_olduname           109
+#define NR_iopl               110
+#define NR_vhangup            111
+#define NR_idle               112
+#define NR_vm86old            113
+#define NR_wait4              114
+#define NR_swapoff            115
+#define NR_sysinfo            116
+#define NR_ipc                117
+#define NR_fsync              118
+#define NR_sigreturn          119
+#define NR_clone              120
+#define NR_setdomainname      121
+#define NR_uname              122
+#define NR_modify_ldt         123
+#define NR_adjtimex           124
+#define NR_mprotect           125
+#define NR_sigprocmask        126
+#define NR_create_module      127
+#define NR_init_module        128
+#define NR_delete_module      129
+#define NR_get_kernel_syms    130
+#define NR_quotactl           131
+#define NR_getpgid            132
+#define NR_fchdir             133
+#define NR_bdflush            134
+#define NR_sysfs              135
+#define NR_personality        136
+#define NR_afs_syscall        137 /* Syscall for Andrew File System */
+#define NR_setfsuid           138
+#define NR_setfsgid           139
+#define NR__llseek            140
+#define NR_getdents           141
+#define NR__newselect         142
+#define NR_flock              143
+#define NR_msync              144
+#define NR_readv              145
+#define NR_writev             146
+#define NR_getsid             147
+#define NR_fdatasync          148
+#define NR__sysctl            149
+#define NR_mlock              150
+#define NR_munlock            151
+#define NR_mlockall           152
+#define NR_munlockall         153
+#define NR_sched_setparam             154
+#define NR_sched_getparam             155
+#define NR_sched_setscheduler         156
+#define NR_sched_getscheduler         157
+#define NR_sched_yield                158
+#define NR_sched_get_priority_max     159
+#define NR_sched_get_priority_min     160
+#define NR_sched_rr_get_interval      161
+#define NR_nanosleep          162
+#define NR_mremap             163
+#define NR_setresuid          164
+#define NR_getresuid          165
+#define NR_vm86               166
+#define NR_query_module       167
+#define NR_poll               168
+#define NR_nfsservctl         169
+#define NR_setresgid          170
+#define NR_getresgid          171
+#define NR_prctl              172
+#define NR_rt_sigreturn       173
+#define NR_rt_sigaction       174
+#define NR_rt_sigprocmask     175
+#define NR_rt_sigpending      176
+#define NR_rt_sigtimedwait    177
+#define NR_rt_sigqueueinfo    178
+#define NR_rt_sigsuspend      179
+#define NR_pread              180
+#define NR_pwrite             181
+#define NR_chown              182
+#define NR_getcwd             183
+#define NR_capget             184
+#define NR_capset             185
+#define NR_sigaltstack        186
+#define NR_sendfile           187
+#define NR_getpmsg            188     /* some people actually want streams */
+#define NR_putpmsg            189     /* some people actually want streams */
+#define NR_vfork              190
+
+typedef long ssize_t;
+typedef unsigned long size_t;
+
+/* Standard file descriptors */
+#define STDIN_FILENO    0  /* Standard input */
+#define STDOUT_FILENO   1  /* Standard output */
+#define STDERR_FILENO   2  /* Standard error output */
+
+static ssize_t write(int fd, const void *buf, size_t count)
+{
+	struct syscall_result res;
+	res = syscall3(NR_write, fd, (unsigned long)buf, count);
+	return res.val;
+}
+
+static void _exit(int status)
+{
+	struct syscall_result res;
+	res = syscall1(NR_exit, status);
+}
+
+static const char *addr_of_char(unsigned char ch)
+{
+	static const char byte[] = {
+		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 
+		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+		0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 
+		0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
+		0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 
+		0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
+		0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 
+		0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
+		0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 
+		0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
+		0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 
+		0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
+		0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 
+		0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
+		0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 
+		0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
+		0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 
+		0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
+		0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 
+		0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
+		0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 
+		0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
+		0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 
+		0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
+		0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 
+		0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
+		0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 
+		0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
+		0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 
+		0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
+		0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 
+		0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
+	};
+	return byte + ch;
+}
+
+static void console_tx_byte(unsigned char ch)
+{
+	write(STDOUT_FILENO, addr_of_char(ch), 1);
+}
+
+static void console_tx_nibble(unsigned nibble)
+{
+	unsigned char digit;
+	digit = nibble + '0';
+	if (digit > '9') {
+		digit += 39;
+	}
+	console_tx_byte(digit);
+}
+
+static void console_tx_char(unsigned char byte)
+{
+	console_tx_byte(byte);
+}
+
+static void console_tx_hex8(unsigned char value)
+{
+	console_tx_nibble((value >> 4U) & 0x0fU);
+	console_tx_nibble(value & 0x0fU);
+}
+
+static void console_tx_hex16(unsigned short value)
+{
+	console_tx_nibble((value >> 12U) & 0x0FU);
+	console_tx_nibble((value >>  8U) & 0x0FU);
+	console_tx_nibble((value >>  4U) & 0x0FU);
+	console_tx_nibble(value & 0x0FU);
+}
+
+static void console_tx_hex32(unsigned short value)
+{
+	console_tx_nibble((value >> 28U) & 0x0FU);
+	console_tx_nibble((value >> 24U) & 0x0FU);
+	console_tx_nibble((value >> 20U) & 0x0FU);
+	console_tx_nibble((value >> 16U) & 0x0FU);
+	console_tx_nibble((value >> 12U) & 0x0FU);
+	console_tx_nibble((value >>  8U) & 0x0FU);
+	console_tx_nibble((value >>  4U) & 0x0FU);
+	console_tx_nibble(value & 0x0FU);
+}
+
+static void console_tx_string(const char *str)
+{
+	unsigned char ch;
+	while((ch = *str++) != '\0') {
+		console_tx_byte(ch);
+	}
+}
+
+static void print_debug_char(unsigned char byte) { console_tx_char(byte); }
+static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); }
+static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); }
+static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); }
+static void print_debug(const char *str) { console_tx_string(str); }
+
+
+static void setup_coherent_ht_domain(void)
+{
+	static const unsigned int register_values[] = {
+#if 1
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x44) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x48) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x4c) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x50) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x54) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x58) & 0xFF)), 0xfff0f0f0, 0x00010101,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x5c) & 0xFF)), 0xfff0f0f0, 0x00010101,
+# 983 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x68) & 0xFF)), 0x00800000, 0x0f00840f,
+# 1005 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4),
+# 1082 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00009c05, 0x11110020,
+# 1127 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x88) & 0xFF)), 0xfffff0ff, 0x00000200,
+# 1148 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x94) & 0xFF)), 0xff000000, 0x00ff0000,
+# 1182 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x003f0000,
+
+
+
+
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007,
+# 1224 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000003,
+
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00400000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00400000,
+# 1276 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00e1ff00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00dfff00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00e3ff00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000b00,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00fe0b00,
+# 1311 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00e00003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00d80003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00e20003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000a03,
+
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00400003,
+# 1350 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x0000d000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x000ff000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000,
+# 1380 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x0000d003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00001013,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000,
+# 1421 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000,
+        ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000,
+#else
+#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
+	(((BUS) & 0xFF) << 16) | \
+	(((DEV) & 0x1f) << 11) | \
+	(((FN) & 0x07) << 8) | \
+	((WHERE) & 0xFF))
+
+	/* Routing Table Node i 
+	 * F0:0x40 i = 0, 
+	 * F0:0x44 i = 1,
+	 * F0:0x48 i = 2, 
+	 * F0:0x4c i = 3,
+	 * F0:0x50 i = 4, 
+	 * F0:0x54 i = 5,
+	 * F0:0x58 i = 6, 
+	 * F0:0x5c i = 7
+	 * [ 0: 3] Request Route
+	 *     [0] Route to this node
+	 *     [1] Route to Link 0
+	 *     [2] Route to Link 1
+	 *     [3] Route to Link 2
+	 * [11: 8] Response Route
+	 *     [0] Route to this node
+	 *     [1] Route to Link 0
+	 *     [2] Route to Link 1
+	 *     [3] Route to Link 2
+	 * [19:16] Broadcast route
+	 *     [0] Route to this node
+	 *     [1] Route to Link 0
+	 *     [2] Route to Link 1
+	 *     [3] Route to Link 2
+	 */
+	PCI_ADDR(0, 0x18, 0, 0x40), 0xfff0f0f0, 0x00010101,
+	PCI_ADDR(0, 0x18, 0, 0x44), 0xfff0f0f0, 0x00010101,
+	PCI_ADDR(0, 0x18, 0, 0x48), 0xfff0f0f0, 0x00010101,
+	PCI_ADDR(0, 0x18, 0, 0x4c), 0xfff0f0f0, 0x00010101,
+	PCI_ADDR(0, 0x18, 0, 0x50), 0xfff0f0f0, 0x00010101,
+	PCI_ADDR(0, 0x18, 0, 0x54), 0xfff0f0f0, 0x00010101,
+	PCI_ADDR(0, 0x18, 0, 0x58), 0xfff0f0f0, 0x00010101,
+	PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101,
+
+	/* Hypetransport Transaction Control Register 
+	 * F0:0x68
+	 * [ 0: 0] Disable read byte probe
+	 *         0 = Probes issues
+	 *         1 = Probes not issued
+	 * [ 1: 1] Disable Read Doubleword probe
+	 *         0 = Probes issued
+	 *         1 = Probes not issued
+	 * [ 2: 2] Disable write byte probes
+	 *         0 = Probes issued
+	 *         1 = Probes not issued
+	 * [ 3: 3] Disable Write Doubleword Probes
+	 *         0 = Probes issued
+	 *         1 = Probes not issued.
+	 * [ 4: 4] Disable Memroy Controller Target Start
+	 *         0 = TgtStart packets are generated
+	 *         1 = TgtStart packets are not generated.
+	 * [ 5: 5] CPU1 Enable
+	 *         0 = Second CPU disabled or not present
+	 *         1 = Second CPU enabled.
+	 * [ 6: 6] CPU Request PassPW
+	 *         0 = CPU requests do not pass posted writes
+	 *         1 = CPU requests pass posted writes.
+	 * [ 7: 7] CPU read Respons PassPW
+	 *         0 = CPU Responses do not pass posted writes
+	 *         1 = CPU responses pass posted writes.
+	 * [ 8: 8] Disable Probe Memory Cancel
+	 *         0 = Probes may generate MemCancels
+	 *         1 = Probes may not generate MemCancels
+	 * [ 9: 9] Disable Remote Probe Memory Cancel.
+	 *         0 = Probes hitting dirty blocks generate memory cancel packets
+	 *         1 = Only probed caches on the same node as the memory controller
+	 *              generate cancel packets.
+	 * [10:10] Disable Fill Probe
+	 *         0 = Probes issued for cache fills
+	 *         1 = Probes not issued for cache fills.
+	 * [11:11] Response PassPw
+	 *         0 = Downstream response PassPW based on original request
+	 *         1 = Downstream response PassPW set to 1
+	 * [12:12] Change ISOC to Ordered
+	 *         0 = Bit 1 of coherent HT RdSz/WrSz command used for iosynchronous prioritization
+	 *         1 = Bit 1 of coherent HT RdSz/WrSz command used for ordering.
+	 * [14:13] Buffer Release Priority select 
+	 *         00 = 64
+	 *         01 = 16
+	 *         10 = 8
+	 *         11 = 2
+	 * [15:15] Limit Coherent HT Configuration Space Range
+	 *         0 = No coherent HT configuration space restrictions
+	 *         1 = Limit coherent HT configuration space based on node count
+	 * [16:16] Local Interrupt Conversion Enable.
+	 *         0 = ExtInt/NMI interrups unaffected.
+	 *         1 = ExtInt/NMI broadcat interrupts converted to LINT0/1
+	 * [17:17] APIC Extended Broadcast Enable.
+	 *         0 = APIC broadcast is 0F
+	 *         1 = APIC broadcast is FF
+	 * [18:18] APIC Extended ID Enable
+	 *         0 = APIC ID is 4 bits.
+	 *         1 = APIC ID is 8 bits.
+	 * [19:19] APIC Extended Spurious Vector Enable
+	 *         0 = Lower 4 bits of spurious vector are read-only 1111
+	 *         1 = Lower 4 bits of spurious vecotr are writeable.
+	 * [20:20] Sequence ID Source Node Enable
+	 *         0 = Normal operation
+	 *         1 = Keep SeqID on routed packets for debugging.
+	 * [22:21] Downstream non-posted request limit
+	 *         00 = No limit
+	 *         01 = Limited to 1
+	 *         10 = Limited to 4
+	 *         11 = Limited to 8
+	 * [23:23] RESERVED
+	 * [25:24] Medium-Priority Bypass Count
+	 *         - Maximum # of times a medium priority access can pass a low
+	 *           priority access before Medium-Priority mode is disabled for one access.
+	 * [27:26] High-Priority Bypass Count
+	 *         - Maximum # of times a high prioirty access can pass a medium or low
+	 *           priority access before High-prioirty mode is disabled for one access.
+	 * [28:28] Enable High Priority CPU Reads
+	 *         0 = Cpu reads are medium prioirty
+	 *         1 = Cpu reads are high prioirty
+	 * [29:29] Disable Low Priority Writes
+	 *         0 = Non-isochronous writes are low priority
+	 *         1 = Non-isochronous writes are medium prioirty
+	 * [30:30] Disable High Priority Isochronous writes
+	 *         0 = Isochronous writes are high priority
+	 *         1 = Isochronous writes are medium priority
+	 * [31:31] Disable Medium Priority Isochronous writes
+	 *         0 = Isochronous writes are medium are high
+	 *         1 = With bit 30 set makes Isochrouns writes low priority.
+	 */
+	PCI_ADDR(0, 0x18, 0, 0x68), 0x00800000, 0x0f00840f,
+	/* HT Initialization Control Register
+	 * F0:0x6C
+	 * [ 0: 0] Routing Table Disable
+	 *         0 = Packets are routed according to routing tables
+	 *         1 = Packets are routed according to the default link field
+	 * [ 1: 1] Request Disable (BSP should clear this)
+	 *         0 = Request packets may be generated
+	 *         1 = Request packets may not be generated.
+	 * [ 3: 2] Default Link (Read-only)
+	 *         00 = LDT0
+	 *         01 = LDT1
+	 *         10 = LDT2
+	 *         11 = CPU on same node
+	 * [ 4: 4] Cold Reset
+	 *         - Scratch bit cleared by a cold reset
+	 * [ 5: 5] BIOS Reset Detect
+	 *         - Scratch bit cleared by a cold reset
+	 * [ 6: 6] INIT Detect
+	 *         - Scratch bit cleared by a warm or cold reset not by an INIT
+	 *
+	 */
+	PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4),
+	/* LDTi Capabilities Registers
+	 * F0:0x80 i = 0,
+	 * F0:0xA0 i = 1,
+	 * F0:0xC0 i = 2,
+	 */
+	/* LDTi Link Control Registrs
+	 * F0:0x84 i = 0,
+	 * F0:0xA4 i = 1,
+	 * F0:0xC4 i = 2,
+	 * [ 1: 1] CRC Flood Enable
+	 *         0 = Do not generate sync packets on CRC error
+	 *         1 = Generate sync packets on CRC error
+	 * [ 2: 2] CRC Start Test (Read-Only)
+	 * [ 3: 3] CRC Force Frame Error
+	 *         0 = Do not generate bad CRC
+	 *         1 = Generate bad CRC
+	 * [ 4: 4] Link Failure
+	 *         0 = No link failure detected
+	 *         1 = Link failure detected
+	 * [ 5: 5] Initialization Complete
+	 *         0 = Initialization not complete
+	 *         1 = Initialization complete
+	 * [ 6: 6] Receiver off
+	 *         0 = Recevier on
+	 *         1 = Receiver off
+	 * [ 7: 7] Transmitter Off
+	 *         0 = Transmitter on
+	 *         1 = Transmitter off
+	 * [ 9: 8] CRC_Error
+	 *         00 = No error
+	 *         [0] = 1 Error on byte lane 0
+	 *         [1] = 1 Error on byte lane 1
+	 * [12:12] Isochrnous Enable  (Read-Only)
+	 * [13:13] HT Stop Tristate Enable
+	 *         0 = Driven during an LDTSTOP_L
+	 *         1 = Tristated during and LDTSTOP_L
+	 * [14:14] Extended CTL Time 
+	 *         0 = CTL is asserted for 16 bit times during link initialization
+	 *         1 = CTL is asserted for 50us during link initialization
+	 * [18:16] Max Link Width In (Read-Only?)
+	 *         000 = 8 bit link
+	 *         001 = 16bit link
+	 * [19:19] Doubleword Flow Control in (Read-Only)
+	 *         0 = This link does not support doubleword flow control
+	 *         1 = This link supports doubleword flow control
+	 * [22:20] Max Link Width Out (Read-Only?)
+	 *         000 = 8 bit link
+	 *         001 = 16bit link
+	 * [23:23] Doubleworld Flow Control out (Read-Only)
+	 *         0 = This link does not support doubleword flow control
+	 *         1 = This link supports doubleworkd flow control
+	 * [26:24] Link Width In
+	 *         000 = Use 8 bits
+	 *         001 = Use 16 bits
+	 *         010 = reserved
+	 *         011 = Use 32 bits
+	 *         100 = Use 2 bits
+	 *         101 = Use 4 bits
+	 *         110 = reserved
+	 *         111 = Link physically not connected
+	 * [27:27] Doubleword Flow Control In Enable
+	 *         0 = Doubleword flow control disabled
+	 *         1 = Doubleword flow control enabled (Not currently supported)
+	 * [30:28] Link Width Out
+	 *         000 = Use 8 bits
+	 *         001 = Use 16 bits
+	 *         010 = reserved
+	 *         011 = Use 32 bits
+	 *         100 = Use 2 bits
+	 *         101 = Use 4 bits
+	 *         110 = reserved
+	 *         111 = Link physically not connected
+	 * [31:31] Doubleworld Flow Control Out Enable
+	 *         0 = Doubleworld flow control disabled
+	 *         1 = Doubleword flow control enabled (Not currently supported)
+	 */
+	PCI_ADDR(0, 0x18, 0, 0x84), 0x00009c05, 0x11110020,
+	/* LDTi Frequency/Revision Registers
+	 * F0:0x88 i = 0,
+	 * F0:0xA8 i = 1,
+	 * F0:0xC8 i = 2,
+	 * [ 4: 0] Minor Revision
+	 *         Contains the HT Minor revision
+	 * [ 7: 5] Major Revision
+	 *         Contains the HT Major revision
+	 * [11: 8] Link Frequency  (Takes effect the next time the link is reconnected)
+	 *         0000 = 200Mhz
+	 *         0001 = reserved
+	 *         0010 = 400Mhz
+	 *         0011 = reserved
+	 *         0100 = 600Mhz
+	 *         0101 = 800Mhz
+	 *         0110 = 1000Mhz
+	 *         0111 = reserved
+	 *         1000 = reserved
+	 *         1001 = reserved
+	 *         1010 = reserved
+	 *         1011 = reserved
+	 *         1100 = reserved
+	 *         1101 = reserved
+	 *         1110 = reserved
+	 *         1111 = 100 Mhz
+	 * [15:12] Error (Not currently Implemented)
+	 * [31:16] Indicates the frequency capabilities of the link
+	 *         [16] = 1 encoding 0000 of freq supported
+	 *         [17] = 1 encoding 0001 of freq supported
+	 *         [18] = 1 encoding 0010 of freq supported
+	 *         [19] = 1 encoding 0011 of freq supported
+	 *         [20] = 1 encoding 0100 of freq supported
+	 *         [21] = 1 encoding 0101 of freq supported
+	 *         [22] = 1 encoding 0110 of freq supported
+	 *         [23] = 1 encoding 0111 of freq supported
+	 *         [24] = 1 encoding 1000 of freq supported
+	 *         [25] = 1 encoding 1001 of freq supported
+	 *         [26] = 1 encoding 1010 of freq supported
+	 *         [27] = 1 encoding 1011 of freq supported
+	 *         [28] = 1 encoding 1100 of freq supported
+	 *         [29] = 1 encoding 1101 of freq supported
+	 *         [30] = 1 encoding 1110 of freq supported
+	 *         [31] = 1 encoding 1111 of freq supported
+	 */
+	PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000200,
+	/* LDTi Feature Capability
+	 * F0:0x8C i = 0,
+	 * F0:0xAC i = 1,
+	 * F0:0xCC i = 2,
+	 */
+	/* LDTi Buffer Count Registers
+	 * F0:0x90 i = 0,
+	 * F0:0xB0 i = 1,
+	 * F0:0xD0 i = 2,
+	 */
+	/* LDTi Bus Number Registers
+	 * F0:0x94 i = 0,
+	 * F0:0xB4 i = 1,
+	 * F0:0xD4 i = 2,
+	 * For NonCoherent HT specifies the bus number downstream (behind the host bridge)
+	 * [ 0: 7] Primary Bus Number
+	 * [15: 8] Secondary Bus Number
+	 * [23:15] Subordiante Bus Number
+	 * [31:24] reserved
+	 */
+	PCI_ADDR(0, 0x18, 0, 0x94), 0xff000000, 0x00ff0000,
+	/* LDTi Type Registers
+	 * F0:0x98 i = 0,
+	 * F0:0xB8 i = 1,
+	 * F0:0xD8 i = 2,
+	 */
+	/* Careful set limit registers before base registers which contain the enables */
+	/* DRAM Limit i Registers
+	 * F1:0x44 i = 0
+	 * F1:0x4C i = 1
+	 * F1:0x54 i = 2
+	 * F1:0x5C i = 3
+	 * F1:0x64 i = 4
+	 * F1:0x6C i = 5
+	 * F1:0x74 i = 6
+	 * F1:0x7C i = 7
+	 * [ 2: 0] Destination Node ID
+	 *         000 = Node 0
+	 *         001 = Node 1
+	 *         010 = Node 2
+	 *         011 = Node 3
+	 *         100 = Node 4
+	 *         101 = Node 5
+	 *         110 = Node 6
+	 *         111 = Node 7
+	 * [ 7: 3] Reserved
+	 * [10: 8] Interleave select
+	 *         specifies the values of A[14:12] to use with interleave enable.
+	 * [15:11] Reserved
+	 * [31:16] DRAM Limit Address i Bits 39-24
+	 *         This field defines the upper address bits of a 40 bit  address
+	 *         that define the end of the DRAM region.
+	 */
+#if MEMORY_1024MB
+	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000,
+#endif
+#if MEMORY_512MB
+	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x001f0000,
+#endif
+	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+	PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+	PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+	PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+	PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+	PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+	PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+	/* DRAM Base i Registers
+	 * F1:0x40 i = 0
+	 * F1:0x48 i = 1
+	 * F1:0x50 i = 2
+	 * F1:0x58 i = 3
+	 * F1:0x60 i = 4
+	 * F1:0x68 i = 5
+	 * F1:0x70 i = 6
+	 * F1:0x78 i = 7
+	 * [ 0: 0] Read Enable
+	 *         0 = Reads Disabled
+	 *         1 = Reads Enabled
+	 * [ 1: 1] Write Enable
+	 *         0 = Writes Disabled
+	 *         1 = Writes Enabled
+	 * [ 7: 2] Reserved
+	 * [10: 8] Interleave Enable
+	 *         000 = No interleave
+	 *         001 = Interleave on A[12] (2 nodes)
+	 *         010 = reserved
+	 *         011 = Interleave on A[12] and A[14] (4 nodes)
+	 *         100 = reserved
+	 *         101 = reserved
+	 *         110 = reserved
+	 *         111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+	 * [15:11] Reserved
+	 * [13:16] DRAM Base Address i Bits 39-24
+	 *         This field defines the upper address bits of a 40-bit address
+	 *         that define the start of the DRAM region.
+	 */
+	PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003,
+#if MEMORY_1024MB
+	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400000,
+	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00400000,
+	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00400000,
+	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00400000,
+	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00400000,
+	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000,
+	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000,
+#endif
+#if MEMORY_512MB
+	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00200000,
+	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200000,
+	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00200000,
+	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00200000,
+	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00200000,
+	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00200000,
+	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00200000,
+#endif
+
+	/* Memory-Mapped I/O Limit i Registers
+	 * F1:0x84 i = 0
+	 * F1:0x8C i = 1
+	 * F1:0x94 i = 2
+	 * F1:0x9C i = 3
+	 * F1:0xA4 i = 4
+	 * F1:0xAC i = 5
+	 * F1:0xB4 i = 6
+	 * F1:0xBC i = 7
+	 * [ 2: 0] Destination Node ID
+	 *         000 = Node 0
+	 *         001 = Node 1
+	 *         010 = Node 2
+	 *         011 = Node 3
+	 *         100 = Node 4
+	 *         101 = Node 5
+	 *         110 = Node 6
+	 *         111 = Node 7
+	 * [ 3: 3] Reserved
+	 * [ 5: 4] Destination Link ID
+	 *         00 = Link 0
+	 *         01 = Link 1
+	 *         10 = Link 2
+	 *         11 = Reserved
+	 * [ 6: 6] Reserved
+	 * [ 7: 7] Non-Posted
+	 *         0 = CPU writes may be posted
+	 *         1 = CPU writes must be non-posted
+	 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+	 *         This field defines the upp adddress bits of a 40-bit address that
+	 *         defines the end of a memory-mapped I/O region n
+	 */
+	PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00,
+	PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00dfff00,
+	PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00e3ff00,
+	PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000b00,
+	PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00fe0b00,
+
+	/* Memory-Mapped I/O Base i Registers
+	 * F1:0x80 i = 0
+	 * F1:0x88 i = 1
+	 * F1:0x90 i = 2
+	 * F1:0x98 i = 3
+	 * F1:0xA0 i = 4
+	 * F1:0xA8 i = 5
+	 * F1:0xB0 i = 6
+	 * F1:0xB8 i = 7
+	 * [ 0: 0] Read Enable
+	 *         0 = Reads disabled
+	 *         1 = Reads Enabled
+	 * [ 1: 1] Write Enable
+	 *         0 = Writes disabled
+	 *         1 = Writes Enabled
+	 * [ 2: 2] Cpu Disable
+	 *         0 = Cpu can use this I/O range
+	 *         1 = Cpu requests do not use this I/O range
+	 * [ 3: 3] Lock
+	 *         0 = base/limit registers i are read/write
+	 *         1 = base/limit registers i are read-only
+	 * [ 7: 4] Reserved
+	 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+	 *         This field defines the upper address bits of a 40bit address 
+	 *         that defines the start of memory-mapped I/O region i
+	 */
+	PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003,
+	PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00d80003,
+	PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00e20003,
+	PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000a03,
+#if MEMORY_1024MB
+	PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00400003,
+#endif
+#if MEMORY_512MB
+	PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00200003,
+#endif
+
+	/* PCI I/O Limit i Registers
+	 * F1:0xC4 i = 0
+	 * F1:0xCC i = 1
+	 * F1:0xD4 i = 2
+	 * F1:0xDC i = 3
+	 * [ 2: 0] Destination Node ID
+	 *         000 = Node 0
+	 *         001 = Node 1
+	 *         010 = Node 2
+	 *         011 = Node 3
+	 *         100 = Node 4
+	 *         101 = Node 5
+	 *         110 = Node 6
+	 *         111 = Node 7
+	 * [ 3: 3] Reserved
+	 * [ 5: 4] Destination Link ID
+	 *         00 = Link 0
+	 *         01 = Link 1
+	 *         10 = Link 2
+	 *         11 = reserved
+	 * [11: 6] Reserved
+	 * [24:12] PCI I/O Limit Address i
+	 *         This field defines the end of PCI I/O region n
+	 * [31:25] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000d000,
+	PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x000ff000,
+	PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+	/* PCI I/O Base i Registers
+	 * F1:0xC0 i = 0
+	 * F1:0xC8 i = 1
+	 * F1:0xD0 i = 2
+	 * F1:0xD8 i = 3
+	 * [ 0: 0] Read Enable
+	 *         0 = Reads Disabled
+	 *         1 = Reads Enabled
+	 * [ 1: 1] Write Enable
+	 *         0 = Writes Disabled
+	 *         1 = Writes Enabled
+	 * [ 3: 2] Reserved
+	 * [ 4: 4] VGA Enable
+	 *         0 = VGA matches Disabled
+	 *         1 = matches all address < 64K and where A[9:0] is in the 
+	 *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+	 * [ 5: 5] ISA Enable
+	 *         0 = ISA matches Disabled
+	 *         1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+	 *             from matching agains this base/limit pair
+	 * [11: 6] Reserved
+	 * [24:12] PCI I/O Base i
+	 *         This field defines the start of PCI I/O region n 
+	 * [31:25] Reserved
+	 */
+	PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003,
+	PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00001013,
+	PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+	/* Config Base and Limit i Registers
+	 * F1:0xE0 i = 0
+	 * F1:0xE4 i = 1
+	 * F1:0xE8 i = 2
+	 * F1:0xEC i = 3
+	 * [ 0: 0] Read Enable
+	 *         0 = Reads Disabled
+	 *         1 = Reads Enabled
+	 * [ 1: 1] Write Enable
+	 *         0 = Writes Disabled
+	 *         1 = Writes Enabled
+	 * [ 2: 2] Device Number Compare Enable
+	 *         0 = The ranges are based on bus number
+	 *         1 = The ranges are ranges of devices on bus 0
+	 * [ 3: 3] Reserved
+	 * [ 6: 4] Destination Node
+	 *         000 = Node 0
+	 *         001 = Node 1
+	 *         010 = Node 2
+	 *         011 = Node 3
+	 *         100 = Node 4
+	 *         101 = Node 5
+	 *         110 = Node 6
+	 *         111 = Node 7
+	 * [ 7: 7] Reserved
+	 * [ 9: 8] Destination Link
+	 *         00 = Link 0
+	 *         01 = Link 1
+	 *         10 = Link 2
+	 *         11 - Reserved
+	 * [15:10] Reserved
+	 * [23:16] Bus Number Base i
+	 *         This field defines the lowest bus number in configuration region i
+	 * [31:24] Bus Number Limit i
+	 *         This field defines the highest bus number in configuration regin i
+	 */
+	PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
+	PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
+#endif
+	};
+	int i;
+	int max;
+	print_debug("setting up coherent ht domain....\r\n");
+	max = sizeof(register_values)/sizeof(register_values[0]);
+	for(i = 0; i < max; i += 3) {
+		unsigned long reg;
+#if 1
+		print_debug_hex32(register_values[i]);
+		print_debug(" <-");
+		print_debug_hex32(register_values[i+2]);
+		print_debug("\r\n");
+#endif
+#if 0
+		reg = pci_read_config32(register_values[i]);
+		reg &= register_values[i+1];
+		reg |= register_values[i+2] & ~register_values[i+1];
+		pci_write_config32(register_values[i], reg);
+#endif
+	}
+	print_debug("done.\r\n");
+}
+
+static void main(void)
+{
+	static const char msg[] = "hello world\r\n";
+#if 0
+	write(STDOUT_FILENO, msg, sizeof(msg));
+#endif
+#if 1
+	setup_coherent_ht_domain();
+#endif
+	_exit(0);
+}
diff --git a/util/romcc/tests/simple_test6.c b/util/romcc/tests/simple_test6.c
index 3dac72d0fb..aba7f1f549 100644
--- a/util/romcc/tests/simple_test6.c
+++ b/util/romcc/tests/simple_test6.c
@@ -260,7 +260,7 @@ static void test(void)
 #if 1
 	outb(m, 0xab);
 #endif
-#if 0
+#if 1
 	outb(n, 0xab);
 #endif
 #if 0