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| author | Mathew King <mathewk@chromium.org> | 2019-10-14 11:37:12 -0600 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-12-02 23:24:08 +0000 |
| commit | 6f8f34f1bf91bd225b1dd9fe4dc70fdcf6ce2805 (patch) | |
| tree | 90c2215787cbaf2a5cba4341a757f7f4d42b635f /util/romcc | |
| parent | f9fa985242b0e4abb089931b7643db4e493bd86f (diff) | |
| download | coreboot-6f8f34f1bf91bd225b1dd9fe4dc70fdcf6ce2805.tar.xz | |
soc/intel/cannonlake: Add gfx.asl file
Add gfx.asl file for cannonlake SOCs to allow for graphics-related ACPI
devices and methods on cannonlake devices.
BUG=b:142237145
TEST=gfx.asl added to drallion dsdt.asl
Change-Id: I38a26f3135d571e2f9b63840d38fd4d3476fc142
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'util/romcc')
0 files changed, 0 insertions, 0 deletions