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authorRizwan Qureshi <rizwan.qureshi@intel.com>2016-11-08 21:01:09 +0530
committerMartin Roth <martinroth@google.com>2016-11-09 23:29:43 +0100
commitd8bb69a451276baf14f17fceeb89790638310990 (patch)
tree7d6a01bc3d36fbcd16b86cbed9d332c0b6b56933 /util/sconfig/sconfig.h
parent1ec0c001793365d8b43f640b2bbc0080b4619d19 (diff)
downloadcoreboot-d8bb69a451276baf14f17fceeb89790638310990.tar.xz
soc/intel/skylake: fix memory access beyond array bounds
chip.h has a config array PcieRpClkReqNumber which corresponds to a FSP UPD parameter, the size is currently set to 20. However the size of PcieRpClkReqNumber UPD in FSP2.0 is 24, so memcpy (config buffer to UPD buffer) in chip_fsp20.c will read beyond the bounds of config array. Hence set the size of PcieRpClkReqNumber array based on the FSP in use. Found-by: Coverity Scan #1365385, #1365386 Change-Id: I937f68ef33f218cd7f9ba5cf3baaec162bca3fc8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/17292 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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