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authorDuncan Laurie <dlaurie@google.com>2018-05-07 14:18:13 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-05-11 08:59:51 +0000
commitbae9f85ddbd2e62af1b47169cbfeb10b06d45e04 (patch)
tree7d02393aa9a757ffaaf33fd4ffc841ddc239e4a7 /util/sconfig/sconfig.y
parent57df0888169a2622e37dfad3694e3de544b8b6fb (diff)
downloadcoreboot-bae9f85ddbd2e62af1b47169cbfeb10b06d45e04.tar.xz
devicetree: Add USB device type
This commit adds support for describing USB ports in devicetree.cb. It allows a USB port location to be described in the tree with configuration information, and ACPI code to be generated that provides this information to the OS. A new scan_usb_bus() is added that will scan bridges for devices so a tree of ports and hubs can be created. The device address is computed with a 'port type' and a 'port id' which is flexible for SOC to handle depending on their specific USB setup and allows USB2 and USB3 ports to be described separately. For example a board may have devices on two ports, one with a USB2 device and one with a USB3 device, both of which are connected to an xHCI controller with a root hub: xHCI | RootHub | | USB2[0] USB3[2] device pci 14.0 on chip drivers/usb/acpi register "name" = ""Root Hub"" device usb 0.0 on chip drivers/usb/acpi register "name" = ""USB 2.0 Port 0"" device usb 2.0 on end end chip drivers/usb/acpi register "name" = ""USB 3.0 Port 2"" device usb 3.2 on end end end end end Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'util/sconfig/sconfig.y')
-rwxr-xr-xutil/sconfig/sconfig.y2
1 files changed, 1 insertions, 1 deletions
diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y
index 05fb751f6e..5cecbbace6 100755
--- a/util/sconfig/sconfig.y
+++ b/util/sconfig/sconfig.y
@@ -29,7 +29,7 @@ static struct device *cur_parent, *cur_bus;
int number;
}
-%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI MMIO
+%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO
%%
devtree: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ;