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| author | Justin TerAvest <teravest@google.com> | 2018-01-17 16:36:30 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-25 16:50:17 +0000 |
| commit | ca2ed9f450682c5f23ee1f3affac8b6dba7fdc0b (patch) | |
| tree | 6c73b52c016bf59eee8d6371793ef479aa75595b /util/sconfig/sconfig.y | |
| parent | 4eaf0fa1550805ba9f3c24fb8675a6e77bd40101 (diff) | |
| download | coreboot-ca2ed9f450682c5f23ee1f3affac8b6dba7fdc0b.tar.xz | |
sconfig: Add a new mmio resource type
Add support for a mmio resource in the devicetree to allow
memory-mapped IO addresses to be assigned to given values.
AMD platforms perform a significant amount of configuration through
these MMIO addresses, including I2C bus configuration.
BUG=b:72121803
Change-Id: I5608721c22c1b229f527815b5f17fff3a080c3c8
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'util/sconfig/sconfig.y')
| -rwxr-xr-x | util/sconfig/sconfig.y | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 7108e67a3a..05fb751f6e 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -29,7 +29,7 @@ static struct device *cur_parent, *cur_bus; int number; } -%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI +%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI MMIO %% devtree: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ; |