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| author | pchandri <preetham.chandrian@intel.com> | 2015-08-14 12:18:31 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-27 14:19:38 +0000 |
| commit | 415022a86c1033e7b233fc2ca16e1d6367425ab5 (patch) | |
| tree | db3f3e7b1e9f7bb35fe66091fc1c00cbf2d40349 /util/scripts | |
| parent | 028bcaae32e8ca779d216dc61a9b3dd468ff4be2 (diff) | |
| download | coreboot-415022a86c1033e7b233fc2ca16e1d6367425ab5.tar.xz | |
skylake: FAB3 Adding Support for various SPD.
This pach enables memory configuration based on PCH_MEM_CFG
and EC_BRD_ID.
BRANCH=None
BUG=chrome-os-partner:44087
CQ-DEPEND=CL:293832
TEST=Build and Boot FAB3 (Kunimitsu)
Original-Change-Id: I7999e609c4b0b3c89a9689ee6bb6b98c88703809
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293787
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I52a1af1683b74e5cad71b9e4861942a23869f255
Signed-off-by: pchandri <preetham.chandrian@intel.com>
Reviewed-on: http://review.coreboot.org/11284
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'util/scripts')
0 files changed, 0 insertions, 0 deletions