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authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-05-24 09:07:04 +0200
committerFelix Held <felix-coreboot@felixheld.de>2019-07-08 16:13:29 +0000
commit674bb3bf65635cc08730be298eeee540efc899bd (patch)
tree649576ffbc672f3ba7e7638023c48ab09b2625da /util/superiotool/superiotool.h
parenta3121b0b2fca0a1f568fe66e5ca3baed1be8acee (diff)
downloadcoreboot-674bb3bf65635cc08730be298eeee540efc899bd.tar.xz
util/superiotool: Add AST2400
Add support for AST2400 Super I/O. The device doesn't have an ID register, so probe for scratch register not to read as 0xff. Tested on platform which has an AST2400. Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'util/superiotool/superiotool.h')
-rw-r--r--util/superiotool/superiotool.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h
index 6e59933792..d3b9fd004c 100644
--- a/util/superiotool/superiotool.h
+++ b/util/superiotool/superiotool.h
@@ -190,6 +190,10 @@ void print_vendor_chips(const char *vendor,
void probe_idregs_ali(uint16_t port);
void print_ali_chips(void);
+/* aspeed.c */
+void probe_idregs_aspeed(uint16_t port);
+void print_aspeed_chips(void);
+
/* amd.c */
void probe_idregs_amd(uint16_t port);
void print_amd_chips(void);
@@ -243,6 +247,7 @@ static const struct {
int ports[MAXNUMPORTS]; /* Signed, as we need EOT. */
} superio_ports_table[] = {
{probe_idregs_ali, {0x3f0, 0x370, EOT}},
+ {probe_idregs_aspeed, {0x2e, 0x4e, EOT}},
{probe_idregs_exar, {0x2e, 0x4e, EOT}},
{probe_idregs_fintek, {0x2e, 0x4e, EOT}},
{probe_idregs_fintek_alternative, {0x2e, 0x4e, EOT}},
@@ -278,6 +283,7 @@ static const struct {
#ifdef PCI_SUPPORT
{print_via_chips},
{print_amd_chips},
+ {print_aspeed_chips},
#endif
{print_serverengines_chips},
{print_infineon_chips},