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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2019-07-09 13:33:04 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-11 15:01:41 +0000 |
| commit | 145748bf25b658da1d2951201413ba9b0c68a266 (patch) | |
| tree | 53e509a8d326382445e36236b2850e1d71bf2c12 /util/viatool/viatool.h | |
| parent | 20cfc87ca07ce1ac07c47480e1a6a5bc0a1e1090 (diff) | |
| download | coreboot-145748bf25b658da1d2951201413ba9b0c68a266.tar.xz | |
mb/google/hatch: Disable GPIO community dynamic clock gating
The dynamic clock gating is causing boards to miss interrupts
whose pulses are shorter than 4us. Disable it using FSP UPDs.
BUG=b:130764684
BRANCH=none
TEST=Compiles
Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'util/viatool/viatool.h')
0 files changed, 0 insertions, 0 deletions