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authorDavid Hendricks <dhendrix@chromium.org>2013-08-26 15:12:12 -0700
committerIsaac Christensen <isaac.christensen@se-eng.com>2014-08-12 22:07:26 +0200
commit42b1b8069c35a4e86772b600ea0264503bf20470 (patch)
tree9e53449e38a72e21a10002ed67e1c753ca66afe0 /util
parent4610f0e64f92639e6992dc242dabbfbfc1cb7453 (diff)
downloadcoreboot-42b1b8069c35a4e86772b600ea0264503bf20470.tar.xz
Exynos5420: ddr3: fine tuning the DDR3 timing values
Fine tuning DDR timings value for better stability * Changed Data Driver Strength from 34 ohms to 30 ohms, expected to enhance signal integrity. * Changed DQ signal from 0xf to 0x1f000f, to keep default value safe. * Changed mrs[2] and added new mrs direct command for setting WL/RL without resetting DLL. * Added explicit reset value write in phy_con0 instead of just setting a bit, to ensure that reset happens. * Added DREX automatic control for ctrl_pd in none read memory state. This is ported from: https://gerrit.chromium.org/gerrit/61405 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I59e96e6dede7b49c6572548aca664d82ad110bb1 Reviewed-on: https://chromium-review.googlesource.com/66995 Reviewed-by: ron minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit ec34b711c6d270672c56d45c370ca14c0aa27ca3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6611 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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