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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-13 09:19:00 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-15 03:56:20 +0000
commit8b72aaf3f723c3be348879bb089cc741c4db73ad (patch)
treeda8968a08c4a5e7f8589d49121fe6e0421868955 /util
parentfbf57596bb1715ebd05bf81e026862a033d62a03 (diff)
downloadcoreboot-8b72aaf3f723c3be348879bb089cc741c4db73ad.tar.xz
util/msrtool: Fix names from IA32_MCO_xx to IA32_MC0_xx
Change-Id: I46cd986f4914b214156da49db37ecfa749386ce8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'util')
-rw-r--r--util/msrtool/intel_atom.c6
-rw-r--r--util/msrtool/intel_core2_later.c6
-rw-r--r--util/msrtool/intel_nehalem.c6
3 files changed, 9 insertions, 9 deletions
diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c
index 2d89c9c640..39e1676e96 100644
--- a/util/msrtool/intel_atom.c
+++ b/util/msrtool/intel_atom.c
@@ -176,13 +176,13 @@ const struct msrdef intel_atom_msrs[] = {
}},
{ BITS_EOT }
}},
- {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", {
+ {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
{ BITS_EOT }
}},
- {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", {
+ {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
{ BITS_EOT }
}},
- {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", {
+ {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
{ BITS_EOT }
}},
{0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {
diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c
index ad353ebc0c..b61f508b4f 100644
--- a/util/msrtool/intel_core2_later.c
+++ b/util/msrtool/intel_core2_later.c
@@ -1057,13 +1057,13 @@ const struct msrdef intel_core2_later_msrs[] = {
}},
{ BITS_EOT }
}},
- {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", {
+ {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
{ BITS_EOT }
}},
- {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", {
+ {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
{ BITS_EOT }
}},
- {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", {
+ {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
{ BITS_EOT }
}},
{0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", {
diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c
index 679efb5f1c..6f99217f1e 100644
--- a/util/msrtool/intel_nehalem.c
+++ b/util/msrtool/intel_nehalem.c
@@ -1621,13 +1621,13 @@ const struct msrdef intel_nehalem_msrs[] = {
}},
{ BITS_EOT }
}},
- {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", {
+ {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
{ BITS_EOT }
}},
- {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", {
+ {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
{ BITS_EOT }
}},
- {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", {
+ {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
{ BITS_EOT }
}},
{0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", {