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authorMartin Roth <martinroth@chromium.org>2021-04-21 16:23:32 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-04-23 15:26:53 +0000
commit7e241bff1883eba2b904cac06497670fd3440953 (patch)
tree36de0888dbd087c6a84f45930afa7444c8adf4bc /util
parent598f2babdcff16698b5928126f7cd8203120a8ea (diff)
downloadcoreboot-7e241bff1883eba2b904cac06497670fd3440953.tar.xz
util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config
The revision B version of the MT53E1G32D2NP-046 memory chip will be used in the next guybrush build. It has a different internal layout than the Revision A part, with 2 ZQ lines per module instead of 1. BUG=b:186027256 TEST=Build only Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I066f40eb890648a9be17cfe0cee20d299000c11a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'util')
-rw-r--r--util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt12
1 files changed, 12 insertions, 0 deletions
diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
index 2cc1fa49b8..3e6eb8bd49 100644
--- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
+++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
@@ -61,6 +61,18 @@
}
},
{
+ "name": "MT53E1G32D2NP-046 WT:B",
+ "attribs": {
+ "densityPerChannelGb": 8,
+ "banks": 8,
+ "channelsPerDie": 2,
+ "diesPerPackage": 2,
+ "bitWidthPerChannel": 16,
+ "ranksPerChannel": 1,
+ "speedMbps": 4267
+ }
+ },
+ {
"name": "H9HKNNNCRMBVAR-NEH",
"attribs": {
"densityPerChannelGb": 8,