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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2021-05-17 19:50:54 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-05-18 17:03:43 +0000 |
| commit | df092c1ded6eaf27ee31f75784b04a37b93f83e1 (patch) | |
| tree | 7c0571c373a67f5ae8aad6b4d6e9f55fbdd6964b /util | |
| parent | a77eb6e6c3d6b83bd63b6ea8dd9b3e22ed985347 (diff) | |
| download | coreboot-df092c1ded6eaf27ee31f75784b04a37b93f83e1.tar.xz | |
soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.asl
We were not adding power management handling of GPIO_COM3 in gpio.asl
This can affect s0ix flow where platform won't go into s0ix since
GPIO_COM3 is not power gated.
BUG=b:188392183
BRANCH=None
TEST=Platform should enter to s0ix and GPIO COMM3 should not block an
entry to s0ix.
Change-Id: I3f269c66bdd6337adb0d2bd29d0b7d72ced19ec4
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'util')
0 files changed, 0 insertions, 0 deletions